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git01.mediatek.com / filogic / uboot / 2de1f36f5dffa4caa233bd57922da19f00f7e7ba / . / arch / arm / dts / mt7987-pinctrl.dtsi
blob: b5e643feffe2b8a7d43c4eddd9a7558be88f25d4 [file] [log] [blame]
developer2de1f362025-01-23 16:55:01 +0800[diff] [blame^]1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright (C) 2023 MediaTek Inc.
4 * Author: Sam.Shih <sam.shih@mediatek.com>
5 */
6
7&pio {
8 mmc_pins_default: mmc-pins-default {
9 mux {
10 function = "flash";
11 groups = "emmc_45";
12 };
13 conf-cmd-dat {
14 pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO",
15 "SPI0_CS", "SPI0_HOLD", "SPI0_WP",
16 "SPI1_CLK", "SPI1_MOSI", "SPI1_MISO";
17 input-enable;
18 drive-strength = <MTK_DRIVE_4mA>;
19 mediatek,pull-up-adv = <1>; /* pull-up 10K */
20 };
21 conf-clk {
22 pins = "SPI1_CS";
23 drive-strength = <MTK_DRIVE_6mA>;
24 mediatek,pull-down-adv = <2>; /* pull-down 50K */
25 };
26 conf-rst {
27 pins = "USB_VBUS";
28 drive-strength = <MTK_DRIVE_4mA>;
29 mediatek,pull-up-adv = <1>; /* pull-up 10K */
30 };
31 };
32
33 mmc_pins_uhs: mmc-pins-uhs {
34 mux {
35 function = "flash";
36 groups = "emmc_45";
37 };
38 conf-cmd-dat {
39 pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO",
40 "SPI0_CS", "SPI0_HOLD", "SPI0_WP",
41 "SPI1_CLK", "SPI1_MOSI", "SPI1_MISO";
42 input-enable;
43 drive-strength = <MTK_DRIVE_4mA>;
44 mediatek,pull-up-adv = <1>; /* pull-up 10K */
45 };
46 conf-clk {
47 pins = "SPI1_CS";
48 drive-strength = <MTK_DRIVE_6mA>;
49 mediatek,pull-down-adv = <2>; /* pull-down 50K */
50 };
51 conf-rst {
52 pins = "USB_VBUS";
53 drive-strength = <MTK_DRIVE_4mA>;
54 mediatek,pull-up-adv = <1>; /* pull-up 10K */
55 };
56 };
57
58 sd_pins_default: sd-pins-default {
59 mux {
60 function = "flash";
61 groups = "sd";
62 };
63 conf-cmd-dat {
64 pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO",
65 "SPI0_CS", "SPI1_MISO";
66 input-enable;
67 drive-strength = <MTK_DRIVE_4mA>;
68 mediatek,pull-up-adv = <1>; /* pull-up 10K */
69 };
70 conf-clk {
71 pins = "SPI1_CS";
72 drive-strength = <MTK_DRIVE_6mA>;
73 mediatek,pull-down-adv = <2>; /* pull-down 50K */
74 };
75 };
76
77 sd_pins_uhs: sd-pins-uhs {
78 mux {
79 function = "flash";
80 groups = "sd";
81 };
82 conf-cmd-dat {
83 pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO",
84 "SPI0_CS", "SPI1_MISO";
85 input-enable;
86 drive-strength = <MTK_DRIVE_4mA>;
87 mediatek,pull-up-adv = <1>; /* pull-up 10K */
88 };
89 conf-clk {
90 pins = "SPI1_CS";
91 drive-strength = <MTK_DRIVE_6mA>;
92 mediatek,pull-down-adv = <2>; /* pull-down 50K */
93 };
94 };
95
96 mdio0_pins: mdio0-pins {
97 mux {
98 function = "eth";
99 groups = "mdc_mdio";
100 };
101
102 conf {
103 groups = "mdc_mdio";
104 drive-strength = <MTK_DRIVE_6mA>;
105 };
106 };
107
108 i2p5gbe_led0_pins: i2p5gbe0-pins {
109 mux {
110 function = "led";
111 groups = "2p5gbe_led0";
112 };
113 };
114
115 i2p5gbe_led1_0_pins: i2p5gbe1-pins {
116 mux {
117 function = "led";
118 groups = "2p5gbe_led1_0";
119 };
120 };
121
122 i2p5gbe_led1_1_pins: i2p5gbe2-pins {
123 mux {
124 function = "led";
125 groups = "2p5gbe_led1_1";
126 };
127 };
128
129 i2c0_pins: i2c0-pins-g2 {
130 mux {
131 function = "i2c";
132 groups = "i2c0_2";
133 };
134 };
135
136 pcie0_pins: pcie0-pins {
137 mux {
138 function = "pcie";
139 groups = "pcie0_pereset", "pcie0_clkreq",
140 "pcie0_wake";
141 };
142 };
143
144 pcie1_pins: pcie1-pins {
145 mux {
146 function = "pcie";
147 groups = "pcie1_pereset", "pcie1_clkreq",
148 "pcie1_wake";
149 };
150 };
151
152 spi0_flash_pins: spi0-pins {
153 mux {
154 function = "spi";
155 groups = "spi0", "spi0_wp_hold";
156 };
157 };
158
159 spic_pins: spi1-pins {
160 mux {
161 function = "spi";
162 groups = "spi1";
163 };
164 };
165
166 spi2_flash_pins: spi2-pins {
167 mux {
168 function = "spi";
169 groups = "spi2", "spi2_wp_hold";
170 };
171 };
172
173 i2c1_pins: i2c1-pins {
174 mux {
175 function = "i2c";
176 groups = "i2c0_2";
177 };
178 };
179
180 i2s_pins: i2s-pins {
181 mux {
182 function = "i2s";
183 groups = "pcm0_1";
184 };
185 };
186
187 pcm_pins: pcm-pins {
188 mux {
189 function = "pcm";
190 groups = "pcm0_1";
191 };
192 };
193
194 uart1_pins: uart1-pins {
195 mux {
196 function = "uart";
197 groups = "uart1_2";
198 };
199 };
200};