blob: f9127ddfbb7dfdaa9b2bfd6040ef9ed2ab1986b3 [file] [log] [blame]
Frank Wunderlich2dd669f2023-10-04 21:04:34 +02001// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Author: Frank Wunderlich <frank-w@public-files.de>
4 *
5 */
6
7/dts-v1/;
8#include <dt-bindings/gpio/gpio.h>
9#include <dt-bindings/leds/common.h>
10#include <dt-bindings/pinctrl/rockchip.h>
11#include <dt-bindings/soc/rockchip,vop2.h>
12#include "rk3568.dtsi"
13
14/ {
15 model = "Bananapi-R2 Pro (RK3568) DDR4 Board";
16 compatible = "rockchip,rk3568-bpi-r2pro", "rockchip,rk3568";
17
18 aliases {
19 ethernet0 = &gmac0;
20 ethernet1 = &gmac1;
21 mmc0 = &sdmmc0;
22 mmc1 = &sdhci;
23 };
24
25 chosen: chosen {
26 stdout-path = "serial2:1500000n8";
27 };
28
29 leds {
30 compatible = "gpio-leds";
31 pinctrl-names = "default";
32 pinctrl-0 = <&blue_led_pin &green_led_pin>;
33
34 blue_led: led-0 {
35 color = <LED_COLOR_ID_BLUE>;
36 default-state = "off";
37 function = LED_FUNCTION_STATUS;
38 gpios = <&gpio0 RK_PD6 GPIO_ACTIVE_HIGH>;
39 };
40
41 green_led: led-1 {
42 color = <LED_COLOR_ID_GREEN>;
43 default-state = "on";
44 function = LED_FUNCTION_POWER;
45 gpios = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>;
46 };
47 };
48
49 dc_12v: dc-12v-regulator {
50 compatible = "regulator-fixed";
51 regulator-name = "dc_12v";
52 regulator-always-on;
53 regulator-boot-on;
54 regulator-min-microvolt = <12000000>;
55 regulator-max-microvolt = <12000000>;
56 };
57
58 hdmi-con {
59 compatible = "hdmi-connector";
60 type = "a";
61
62 port {
63 hdmi_con_in: endpoint {
64 remote-endpoint = <&hdmi_out_con>;
65 };
66 };
67 };
68
69 ir-receiver {
70 compatible = "gpio-ir-receiver";
71 gpios = <&gpio0 RK_PC2 GPIO_ACTIVE_LOW>;
72 pinctrl-names = "default";
73 pinctrl-0 = <&ir_receiver_pin>;
74 };
75
76 vcc3v3_sys: vcc3v3-sys-regulator {
77 compatible = "regulator-fixed";
78 regulator-name = "vcc3v3_sys";
79 regulator-always-on;
80 regulator-boot-on;
81 regulator-min-microvolt = <3300000>;
82 regulator-max-microvolt = <3300000>;
83 vin-supply = <&dc_12v>;
84 };
85
86 vcc5v0_sys: vcc5v0-sys-regulator {
87 compatible = "regulator-fixed";
88 regulator-name = "vcc5v0_sys";
89 regulator-always-on;
90 regulator-boot-on;
91 regulator-min-microvolt = <5000000>;
92 regulator-max-microvolt = <5000000>;
93 vin-supply = <&dc_12v>;
94 };
95
96 pcie30_avdd0v9: pcie30-avdd0v9-regulator {
97 compatible = "regulator-fixed";
98 regulator-name = "pcie30_avdd0v9";
99 regulator-always-on;
100 regulator-boot-on;
101 regulator-min-microvolt = <900000>;
102 regulator-max-microvolt = <900000>;
103 vin-supply = <&vcc3v3_sys>;
104 };
105
106 pcie30_avdd1v8: pcie30-avdd1v8-regulator {
107 compatible = "regulator-fixed";
108 regulator-name = "pcie30_avdd1v8";
109 regulator-always-on;
110 regulator-boot-on;
111 regulator-min-microvolt = <1800000>;
112 regulator-max-microvolt = <1800000>;
113 vin-supply = <&vcc3v3_sys>;
114 };
115
116 /* pi6c pcie clock generator feeds both ports */
117 vcc3v3_pi6c_05: vcc3v3-pi6c-05-regulator {
118 compatible = "regulator-fixed";
119 regulator-name = "vcc3v3_pcie";
120 regulator-min-microvolt = <3300000>;
121 regulator-max-microvolt = <3300000>;
122 enable-active-high;
123 gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;
124 startup-delay-us = <200000>;
125 vin-supply = <&vcc5v0_sys>;
126 };
127
128 /* actually fed by vcc3v3_sys, dependent on pi6c clock generator */
129 vcc3v3_minipcie: vcc3v3-minipcie-regulator {
130 compatible = "regulator-fixed";
131 regulator-name = "vcc3v3_minipcie";
132 regulator-min-microvolt = <3300000>;
133 regulator-max-microvolt = <3300000>;
134 enable-active-high;
135 gpio = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>;
136 pinctrl-names = "default";
137 pinctrl-0 = <&minipcie_enable_h>;
138 startup-delay-us = <50000>;
139 vin-supply = <&vcc3v3_pi6c_05>;
140 };
141
142 /* actually fed by vcc3v3_sys, dependent on pi6c clock generator */
143 vcc3v3_ngff: vcc3v3-ngff-regulator {
144 compatible = "regulator-fixed";
145 regulator-name = "vcc3v3_ngff";
146 regulator-min-microvolt = <3300000>;
147 regulator-max-microvolt = <3300000>;
148 enable-active-high;
149 gpio = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>;
150 pinctrl-names = "default";
151 pinctrl-0 = <&ngffpcie_enable_h>;
152 startup-delay-us = <50000>;
153 vin-supply = <&vcc3v3_pi6c_05>;
154 };
155
156 vcc5v0_usb: vcc5v0-usb-regulator {
157 compatible = "regulator-fixed";
158 regulator-name = "vcc5v0_usb";
159 regulator-always-on;
160 regulator-boot-on;
161 regulator-min-microvolt = <5000000>;
162 regulator-max-microvolt = <5000000>;
163 vin-supply = <&dc_12v>;
164 };
165
166 vcc5v0_usb_host: vcc5v0-usb-host-regulator {
167 compatible = "regulator-fixed";
168 enable-active-high;
169 gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
170 pinctrl-names = "default";
171 pinctrl-0 = <&vcc5v0_usb_host_en>;
172 regulator-name = "vcc5v0_usb_host";
173 regulator-min-microvolt = <5000000>;
174 regulator-max-microvolt = <5000000>;
175 vin-supply = <&vcc5v0_usb>;
176 };
177
178 vcc5v0_usb_otg: vcc5v0-usb-otg-regulator {
179 compatible = "regulator-fixed";
180 enable-active-high;
181 gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
182 pinctrl-names = "default";
183 pinctrl-0 = <&vcc5v0_usb_otg_en>;
184 regulator-name = "vcc5v0_usb_otg";
185 regulator-min-microvolt = <5000000>;
186 regulator-max-microvolt = <5000000>;
187 vin-supply = <&vcc5v0_usb>;
188 };
189};
190
191&combphy0 {
192 /* used for USB3 */
193 status = "okay";
194};
195
196&combphy1 {
197 /* used for USB3 */
198 status = "okay";
199};
200
201&combphy2 {
202 /* used for SATA */
203 status = "okay";
204};
205
206&gmac0 {
207 assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
208 assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&cru CLK_MAC0_2TOP>;
209 clock_in_out = "input";
210 phy-mode = "rgmii";
211 pinctrl-names = "default";
212 pinctrl-0 = <&gmac0_miim
213 &gmac0_tx_bus2
214 &gmac0_rx_bus2
215 &gmac0_rgmii_clk
216 &gmac0_rgmii_bus>;
217 snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
218 snps,reset-active-low;
219 /* Reset time is 20ms, 100ms for rtl8211f */
220 snps,reset-delays-us = <0 20000 100000>;
221 tx_delay = <0x4f>;
222 rx_delay = <0x0f>;
223 status = "okay";
224
225 fixed-link {
226 speed = <1000>;
227 full-duplex;
228 pause;
229 };
230};
231
232&gmac1 {
233 assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
234 assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_2TOP>;
235 clock_in_out = "output";
236 phy-handle = <&rgmii_phy1>;
237 phy-mode = "rgmii";
238 pinctrl-names = "default";
239 pinctrl-0 = <&gmac1m1_miim
240 &gmac1m1_tx_bus2
241 &gmac1m1_rx_bus2
242 &gmac1m1_rgmii_clk
243 &gmac1m1_rgmii_bus>;
244
245 snps,reset-gpio = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>;
246 snps,reset-active-low;
247 /* Reset time is 20ms, 100ms for rtl8211f */
248 snps,reset-delays-us = <0 20000 100000>;
249
250 tx_delay = <0x3c>;
251 rx_delay = <0x2f>;
252
253 status = "okay";
254};
255
256&gpu {
257 mali-supply = <&vdd_gpu>;
258 status = "okay";
259};
260
261&hdmi {
262 avdd-0v9-supply = <&vdda0v9_image>;
263 avdd-1v8-supply = <&vcca1v8_image>;
264 status = "okay";
265};
266
267&hdmi_in {
268 hdmi_in_vp0: endpoint {
269 remote-endpoint = <&vp0_out_hdmi>;
270 };
271};
272
273&hdmi_out {
274 hdmi_out_con: endpoint {
275 remote-endpoint = <&hdmi_con_in>;
276 };
277};
278
279&hdmi_sound {
280 status = "okay";
281};
282
283&i2c0 {
284 status = "okay";
285
286 rk809: pmic@20 {
287 compatible = "rockchip,rk809";
288 reg = <0x20>;
289 interrupt-parent = <&gpio0>;
290 interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
291 #clock-cells = <1>;
292 pinctrl-names = "default";
293 pinctrl-0 = <&pmic_int>;
294 rockchip,system-power-controller;
295 vcc1-supply = <&vcc3v3_sys>;
296 vcc2-supply = <&vcc3v3_sys>;
297 vcc3-supply = <&vcc3v3_sys>;
298 vcc4-supply = <&vcc3v3_sys>;
299 vcc5-supply = <&vcc3v3_sys>;
300 vcc6-supply = <&vcc3v3_sys>;
301 vcc7-supply = <&vcc3v3_sys>;
302 vcc8-supply = <&vcc3v3_sys>;
303 vcc9-supply = <&vcc3v3_sys>;
304 wakeup-source;
305
306 regulators {
307 vdd_logic: DCDC_REG1 {
308 regulator-name = "vdd_logic";
309 regulator-always-on;
310 regulator-boot-on;
311 regulator-initial-mode = <0x2>;
312 regulator-min-microvolt = <500000>;
313 regulator-max-microvolt = <1350000>;
314 regulator-ramp-delay = <6001>;
315
316 regulator-state-mem {
317 regulator-off-in-suspend;
318 };
319 };
320
321 vdd_gpu: DCDC_REG2 {
322 regulator-name = "vdd_gpu";
323 regulator-always-on;
324 regulator-initial-mode = <0x2>;
325 regulator-min-microvolt = <500000>;
326 regulator-max-microvolt = <1350000>;
327 regulator-ramp-delay = <6001>;
328
329 regulator-state-mem {
330 regulator-off-in-suspend;
331 };
332 };
333
334 vcc_ddr: DCDC_REG3 {
335 regulator-name = "vcc_ddr";
336 regulator-always-on;
337 regulator-boot-on;
338 regulator-initial-mode = <0x2>;
339
340 regulator-state-mem {
341 regulator-on-in-suspend;
342 };
343 };
344
345 vdd_npu: DCDC_REG4 {
346 regulator-name = "vdd_npu";
347 regulator-initial-mode = <0x2>;
348 regulator-min-microvolt = <500000>;
349 regulator-max-microvolt = <1350000>;
350 regulator-ramp-delay = <6001>;
351
352 regulator-state-mem {
353 regulator-off-in-suspend;
354 };
355 };
356
357 vcc_1v8: DCDC_REG5 {
358 regulator-name = "vcc_1v8";
359 regulator-always-on;
360 regulator-boot-on;
361 regulator-min-microvolt = <1800000>;
362 regulator-max-microvolt = <1800000>;
363
364 regulator-state-mem {
365 regulator-off-in-suspend;
366 };
367 };
368
369 vdda0v9_image: LDO_REG1 {
370 regulator-name = "vdda0v9_image";
371 regulator-always-on;
372 regulator-min-microvolt = <900000>;
373 regulator-max-microvolt = <900000>;
374
375 regulator-state-mem {
376 regulator-off-in-suspend;
377 };
378 };
379
380 vdda_0v9: LDO_REG2 {
381 regulator-name = "vdda_0v9";
382 regulator-always-on;
383 regulator-boot-on;
384 regulator-min-microvolt = <900000>;
385 regulator-max-microvolt = <900000>;
386
387 regulator-state-mem {
388 regulator-off-in-suspend;
389 };
390 };
391
392 vdda0v9_pmu: LDO_REG3 {
393 regulator-name = "vdda0v9_pmu";
394 regulator-always-on;
395 regulator-boot-on;
396 regulator-min-microvolt = <900000>;
397 regulator-max-microvolt = <900000>;
398
399 regulator-state-mem {
400 regulator-on-in-suspend;
401 regulator-suspend-microvolt = <900000>;
402 };
403 };
404
405 vccio_acodec: LDO_REG4 {
406 regulator-name = "vccio_acodec";
407 regulator-always-on;
408 regulator-boot-on;
409 regulator-min-microvolt = <3300000>;
410 regulator-max-microvolt = <3300000>;
411
412 regulator-state-mem {
413 regulator-off-in-suspend;
414 };
415 };
416
417 vccio_sd: LDO_REG5 {
418 regulator-name = "vccio_sd";
419 regulator-min-microvolt = <1800000>;
420 regulator-max-microvolt = <3300000>;
421
422 regulator-state-mem {
423 regulator-off-in-suspend;
424 };
425 };
426
427 vcc3v3_pmu: LDO_REG6 {
428 regulator-name = "vcc3v3_pmu";
429 regulator-always-on;
430 regulator-boot-on;
431 regulator-min-microvolt = <3300000>;
432 regulator-max-microvolt = <3300000>;
433
434 regulator-state-mem {
435 regulator-on-in-suspend;
436 regulator-suspend-microvolt = <3300000>;
437 };
438 };
439
440 vcca_1v8: LDO_REG7 {
441 regulator-name = "vcca_1v8";
442 regulator-always-on;
443 regulator-boot-on;
444 regulator-min-microvolt = <1800000>;
445 regulator-max-microvolt = <1800000>;
446
447 regulator-state-mem {
448 regulator-off-in-suspend;
449 };
450 };
451
452 vcca1v8_pmu: LDO_REG8 {
453 regulator-name = "vcca1v8_pmu";
454 regulator-always-on;
455 regulator-boot-on;
456 regulator-min-microvolt = <1800000>;
457 regulator-max-microvolt = <1800000>;
458
459 regulator-state-mem {
460 regulator-on-in-suspend;
461 regulator-suspend-microvolt = <1800000>;
462 };
463 };
464
465 vcca1v8_image: LDO_REG9 {
466 regulator-name = "vcca1v8_image";
467 regulator-always-on;
468 regulator-min-microvolt = <1800000>;
469 regulator-max-microvolt = <1800000>;
470
471 regulator-state-mem {
472 regulator-off-in-suspend;
473 };
474 };
475
476 vcc_3v3: SWITCH_REG1 {
477 regulator-name = "vcc_3v3";
478 regulator-always-on;
479 regulator-boot-on;
480
481 regulator-state-mem {
482 regulator-off-in-suspend;
483 };
484 };
485
486 vcc3v3_sd: SWITCH_REG2 {
487 regulator-name = "vcc3v3_sd";
488 regulator-always-on;
489
490 regulator-state-mem {
491 regulator-off-in-suspend;
492 };
493 };
494 };
495 };
496};
497
498&i2c3 {
499 status = "okay";
500
501 hym8563: rtc@51 {
502 compatible = "haoyu,hym8563";
503 reg = <0x51>;
504 interrupt-parent = <&gpio0>;
505 interrupts = <RK_PD3 IRQ_TYPE_EDGE_FALLING>;
506 #clock-cells = <0>;
507 clock-output-names = "rtcic_32kout";
508 pinctrl-names = "default";
509 pinctrl-0 = <&hym8563_int>;
510 wakeup-source;
511 };
512};
513
514&i2c5 {
515 /* pin 3 (SDA) + 4 (SCL) of header con2 */
516 status = "disabled";
517};
518
519&i2s0_8ch {
520 /* hdmi sound */
521 status = "okay";
522};
523
524&mdio0 {
525 #address-cells = <1>;
526 #size-cells = <0>;
527
528 switch@0 {
529 compatible = "mediatek,mt7531";
530 reg = <0>;
531
532 ports {
533 #address-cells = <1>;
534 #size-cells = <0>;
535
536 port@1 {
537 reg = <1>;
538 label = "lan0";
539 };
540
541 port@2 {
542 reg = <2>;
543 label = "lan1";
544 };
545
546 port@3 {
547 reg = <3>;
548 label = "lan2";
549 };
550
551 port@4 {
552 reg = <4>;
553 label = "lan3";
554 };
555
556 port@5 {
557 reg = <5>;
558 label = "cpu";
559 ethernet = <&gmac0>;
560 phy-mode = "rgmii";
561
562 fixed-link {
563 speed = <1000>;
564 full-duplex;
565 pause;
566 };
567 };
568 };
569 };
570};
571
572&mdio1 {
573 rgmii_phy1: ethernet-phy@0 {
574 compatible = "ethernet-phy-ieee802.3-c22";
575 reg = <0x0>;
576 };
577};
578
579&pcie30phy {
580 data-lanes = <1 2>;
581 phy-supply = <&vcc3v3_pi6c_05>;
582 status = "okay";
583};
584
585&pcie3x1 {
586 /* M.2 slot */
587 num-lanes = <1>;
588 pinctrl-names = "default";
589 pinctrl-0 = <&ngffpcie_reset_h>;
590 reset-gpios = <&gpio3 RK_PA1 GPIO_ACTIVE_HIGH>;
591 vpcie3v3-supply = <&vcc3v3_ngff>;
592 status = "okay";
593};
594
595&pcie3x2 {
596 /* mPCIe slot */
597 num-lanes = <1>;
598 pinctrl-names = "default";
599 pinctrl-0 = <&minipcie_reset_h>;
600 reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;
601 vpcie3v3-supply = <&vcc3v3_minipcie>;
602 status = "okay";
603};
604
605&pinctrl {
606 leds {
607 blue_led_pin: blue-led-pin {
608 rockchip,pins = <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
609 };
610 green_led_pin: green-led-pin {
611 rockchip,pins = <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
612 };
613 };
614
615 hym8563 {
616 hym8563_int: hym8563-int {
617 rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
618 };
619 };
620
621 ir-receiver {
622 ir_receiver_pin: ir-receiver-pin {
623 rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
624 };
625 };
626
627 pcie {
628 minipcie_enable_h: minipcie-enable-h {
629 rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none_drv_level_5>;
630 };
631
632 ngffpcie_enable_h: ngffpcie-enable-h {
633 rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none_drv_level_5>;
634 };
635
636 minipcie_reset_h: minipcie-reset-h {
637 rockchip,pins = <2 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none_drv_level_5>;
638 };
639
640 ngffpcie_reset_h: ngffpcie-reset-h {
641 rockchip,pins = <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none_drv_level_5>;
642 };
643 };
644
645 pmic {
646 pmic_int: pmic_int {
647 rockchip,pins =
648 <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
649 };
650 };
651
652 usb {
653 vcc5v0_usb_host_en: vcc5v0_usb_host_en {
654 rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
655 };
656
657 vcc5v0_usb_otg_en: vcc5v0_usb_otg_en {
658 rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
659 };
660 };
661};
662
663&pmu_io_domains {
664 pmuio1-supply = <&vcc3v3_pmu>;
665 pmuio2-supply = <&vcc3v3_pmu>;
666 vccio1-supply = <&vccio_acodec>;
667 vccio3-supply = <&vccio_sd>;
668 vccio4-supply = <&vcc_3v3>;
669 vccio5-supply = <&vcc_3v3>;
670 vccio6-supply = <&vcc_1v8>;
671 vccio7-supply = <&vcc_3v3>;
672 status = "okay";
673};
674
675&pwm8 {
676 /* fan 5v - gnd - pwm */
677 status = "okay";
678};
679
680&pwm10 {
681 /* pin 7 of header con2 */
682 status = "disabled";
683};
684
685&pwm11 {
686 /* pin 15 of header con2 */
687 status = "disabled";
688};
689
690&pwm12 {
691 /* pin 21 of header con2 */
692 /* shared with uart9 + spi3 */
693 pinctrl-0 = <&pwm12m1_pins>;
694 status = "disabled";
695};
696
697&pwm13 {
698 /* pin 24 of header con2 */
699 /* shared with uart9 */
700 pinctrl-0 = <&pwm13m1_pins>;
701 status = "disabled";
702};
703
704&pwm14 {
705 /* pin 23 of header con2 */
706 /* shared with spi3 */
707 pinctrl-0 = <&pwm14m1_pins>;
708 status = "disabled";
709};
710
711&pwm15 {
712 /* pin 19 of header con2 */
713 /* shared with spi3 */
714 pinctrl-0 = <&pwm15m1_pins>;
715 status = "disabled";
716};
717
718&saradc {
719 vref-supply = <&vcca_1v8>;
720 status = "okay";
721};
722
723&sata2 {
724 status = "okay";
725};
726
727&sdhci {
728 bus-width = <8>;
729 max-frequency = <200000000>;
730 non-removable;
731 pinctrl-names = "default";
732 pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>;
733 status = "okay";
734};
735
736&sdmmc0 {
737 bus-width = <4>;
738 cap-sd-highspeed;
739 cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
740 disable-wp;
741 pinctrl-names = "default";
742 pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
743 sd-uhs-sdr104;
744 vmmc-supply = <&vcc3v3_sd>;
745 vqmmc-supply = <&vccio_sd>;
746 status = "okay";
747};
748
749&spi3 {
750 /* pin 19 (MO) + 21 (MI) + 23 (CK) of header con2 */
751 /* shared with pwm12/14/15 and uart9 */
752 pinctrl-0 = <&spi3m1_pins>;
753 status = "disabled";
754};
755
756&tsadc {
757 rockchip,hw-tshut-mode = <1>;
758 rockchip,hw-tshut-polarity = <0>;
759 status = "okay";
760};
761
762&uart0 {
763 /* pin 8 (TX) + 10 (RX) (RTS:16, CTS:18) of header con2 */
764 status = "disabled";
765};
766
767&uart2 {
768 /* debug-uart */
769 status = "okay";
770};
771
772&uart7 {
773 /* pin 11 (TX) + 13 (RX) of header con2 */
774 pinctrl-0 = <&uart7m1_xfer>;
775 status = "disabled";
776};
777
778&uart9 {
779 /* pin 21 (TX) + 24 (RX) of header con2 */
780 /* shared with pwm13 and pwm12/spi3 */
781 pinctrl-0 = <&uart9m1_xfer>;
782 status = "disabled";
783};
784
785&usb_host0_ehci {
786 status = "okay";
787};
788
789&usb_host0_ohci {
790 status = "okay";
791};
792
793&usb_host0_xhci {
794 dr_mode = "host";
795 status = "okay";
796};
797
798&usb_host1_ehci {
799 status = "okay";
800};
801
802&usb_host1_ohci {
803 status = "okay";
804};
805
806&usb_host1_xhci {
807 status = "okay";
808};
809
810&usb2phy0 {
811 status = "okay";
812};
813
814&usb2phy0_host {
815 phy-supply = <&vcc5v0_usb_host>;
816 status = "okay";
817};
818
819&usb2phy0_otg {
820 phy-supply = <&vcc5v0_usb_otg>;
821 status = "okay";
822};
823
824&usb2phy1 {
825 /* USB for PCIe/M2 */
826 status = "okay";
827};
828
829&usb2phy1_host {
830 status = "okay";
831};
832
833&usb2phy1_otg {
834 status = "okay";
835};
836
837&vop {
838 assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
839 assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
840 status = "okay";
841};
842
843&vop_mmu {
844 status = "okay";
845};
846
847&vp0 {
848 vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
849 reg = <ROCKCHIP_VOP2_EP_HDMI0>;
850 remote-endpoint = <&hdmi_in_vp0>;
851 };
852};