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Gregory CLEMENTb622f8f2018-12-14 16:16:49 +01001// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (c) 2018 Microsemi Corporation
4 */
5
6#include <common.h>
Simon Glass2dc9c342020-05-10 11:40:01 -06007#include <image.h>
Simon Glassa7b51302019-11-14 12:57:46 -07008#include <init.h>
Gregory CLEMENTb622f8f2018-12-14 16:16:49 +01009#include <asm/io.h>
10#include <asm/addrspace.h>
11#include <asm/types.h>
Gregory CLEMENTb622f8f2018-12-14 16:16:49 +010012#include <spi.h>
Lars Povlsenc89dc232019-01-02 09:52:26 +010013#include <led.h>
Gregory CLEMENT550ee062019-01-17 17:07:14 +010014#include <wait_bit.h>
Horatiu Vultur41935df2019-04-24 11:27:58 +020015#include <miiphy.h>
Gregory CLEMENTb622f8f2018-12-14 16:16:49 +010016
17DECLARE_GLOBAL_DATA_PTR;
18
Lars Povlsen90392822018-12-20 09:56:05 +010019enum {
20 BOARD_TYPE_PCB120 = 0xAABBCC00,
21 BOARD_TYPE_PCB123,
22};
Gregory CLEMENTb622f8f2018-12-14 16:16:49 +010023
Gregory CLEMENT550ee062019-01-17 17:07:14 +010024void mscc_switch_reset(bool enter)
25{
26 /* Nasty workaround to avoid GPIO19 (DDR!) being reset */
27 mscc_gpio_set_alternate(19, 2);
28
29 debug("applying SwC reset\n");
30
31 writel(ICPU_RESET_CORE_RST_PROTECT, BASE_CFG + ICPU_RESET);
32 writel(PERF_SOFT_RST_SOFT_CHIP_RST, BASE_DEVCPU_GCB + PERF_SOFT_RST);
33
34 if (wait_for_bit_le32(BASE_DEVCPU_GCB + PERF_SOFT_RST,
35 PERF_SOFT_RST_SOFT_CHIP_RST, false, 5000, false))
36 pr_err("Tiemout while waiting for switch reset\n");
37
38 /*
39 * Reset GPIO19 mode back as regular GPIO, output, high (DDR
40 * not reset) (Order is important)
41 */
42 setbits_le32(BASE_DEVCPU_GCB + PERF_GPIO_OE, BIT(19));
43 writel(BIT(19), BASE_DEVCPU_GCB + PERF_GPIO_OUT_SET);
44 mscc_gpio_set_alternate(19, 0);
45}
46
Horatiu Vultur41935df2019-04-24 11:27:58 +020047int board_phy_config(struct phy_device *phydev)
48{
49 if (gd->board_type == BOARD_TYPE_PCB123)
50 return 0;
51
52 phy_write(phydev, 0, 31, 0x10);
53 phy_write(phydev, 0, 18, 0x80F0);
54 while (phy_read(phydev, 0, 18) & 0x8000)
55 ;
56 phy_write(phydev, 0, 31, 0);
57
58 return 0;
59}
60
Gregory CLEMENTb622f8f2018-12-14 16:16:49 +010061void board_debug_uart_init(void)
62{
63 /* too early for the pinctrl driver, so configure the UART pins here */
Lars Povlsen90392822018-12-20 09:56:05 +010064 mscc_gpio_set_alternate(6, 1);
65 mscc_gpio_set_alternate(7, 1);
Gregory CLEMENTb622f8f2018-12-14 16:16:49 +010066}
67
68int board_early_init_r(void)
69{
70 /* Prepare SPI controller to be used in master mode */
71 writel(0, BASE_CFG + ICPU_SW_MODE);
72 clrsetbits_le32(BASE_CFG + ICPU_GENERAL_CTRL,
73 ICPU_GENERAL_CTRL_IF_SI_OWNER_M,
74 ICPU_GENERAL_CTRL_IF_SI_OWNER(2));
75
76 /* Address of boot parameters */
77 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE;
Lars Povlsenc89dc232019-01-02 09:52:26 +010078
79 /* LED setup */
80 if (IS_ENABLED(CONFIG_LED))
81 led_default_state();
82
Gregory CLEMENTb622f8f2018-12-14 16:16:49 +010083 return 0;
84}
Lars Povlsen90392822018-12-20 09:56:05 +010085
86static void do_board_detect(void)
87{
88 u16 dummy = 0;
89
90 /* Enable MIIM */
91 mscc_gpio_set_alternate(14, 1);
92 mscc_gpio_set_alternate(15, 1);
93 if (mscc_phy_rd(1, 0, 0, &dummy) == 0)
94 gd->board_type = BOARD_TYPE_PCB120;
95 else
96 gd->board_type = BOARD_TYPE_PCB123;
97}
98
99#if defined(CONFIG_MULTI_DTB_FIT)
100int board_fit_config_name_match(const char *name)
101{
102 if (gd->board_type == BOARD_TYPE_PCB120 &&
103 strcmp(name, "ocelot_pcb120") == 0)
104 return 0;
105
106 if (gd->board_type == BOARD_TYPE_PCB123 &&
107 strcmp(name, "ocelot_pcb123") == 0)
108 return 0;
109
110 return -1;
111}
112#endif
113
114#if defined(CONFIG_DTB_RESELECT)
115int embedded_dtb_select(void)
116{
117 do_board_detect();
118 fdtdec_setup();
119
120 return 0;
121}
122#endif