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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0 */
Nobuhiro Iwamatsu4a495bc2013-11-21 17:07:45 +09002/*
3 * arch/arm/include/asm/arch-rmobile/r8a7791.h
Nobuhiro Iwamatsu4a495bc2013-11-21 17:07:45 +09004 *
Nobuhiro Iwamatsu52b96742014-03-27 16:11:17 +09005 * Copyright (C) 2013,2014 Renesas Electronics Corporation
Tom Rini10e47792018-05-06 17:58:06 -04006 */
Nobuhiro Iwamatsu4a495bc2013-11-21 17:07:45 +09007
8#ifndef __ASM_ARCH_R8A7791_H
9#define __ASM_ARCH_R8A7791_H
10
Nobuhiro Iwamatsu52b96742014-03-27 16:11:17 +090011#include "rcar-base.h"
Nobuhiro Iwamatsu4a495bc2013-11-21 17:07:45 +090012/*
Nobuhiro Iwamatsu52b96742014-03-27 16:11:17 +090013 * R-Car (R8A7791) I/O Addresses
Nobuhiro Iwamatsu4a495bc2013-11-21 17:07:45 +090014 */
Nobuhiro Iwamatsudc2c4f02014-11-06 16:03:47 +090015
16/* SH-I2C */
17#define CONFIG_SYS_I2C_SH_BASE2 0xE60B0000
18
Nobuhiro Iwamatsu3ec5f862014-12-17 08:03:00 +090019/* SDHI */
20#define CONFIG_SYS_SH_SDHI1_BASE 0xEE140000
21#define CONFIG_SYS_SH_SDHI2_BASE 0xEE160000
22#define CONFIG_SYS_SH_SDHI_NR_CHANNEL 3
23
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +090024#define DBSC3_1_QOS_R0_BASE 0xE67A1000
25#define DBSC3_1_QOS_R1_BASE 0xE67A1100
26#define DBSC3_1_QOS_R2_BASE 0xE67A1200
27#define DBSC3_1_QOS_R3_BASE 0xE67A1300
28#define DBSC3_1_QOS_R4_BASE 0xE67A1400
29#define DBSC3_1_QOS_R5_BASE 0xE67A1500
30#define DBSC3_1_QOS_R6_BASE 0xE67A1600
31#define DBSC3_1_QOS_R7_BASE 0xE67A1700
32#define DBSC3_1_QOS_R8_BASE 0xE67A1800
33#define DBSC3_1_QOS_R9_BASE 0xE67A1900
34#define DBSC3_1_QOS_R10_BASE 0xE67A1A00
35#define DBSC3_1_QOS_R11_BASE 0xE67A1B00
36#define DBSC3_1_QOS_R12_BASE 0xE67A1C00
37#define DBSC3_1_QOS_R13_BASE 0xE67A1D00
38#define DBSC3_1_QOS_R14_BASE 0xE67A1E00
39#define DBSC3_1_QOS_R15_BASE 0xE67A1F00
40#define DBSC3_1_QOS_W0_BASE 0xE67A2000
41#define DBSC3_1_QOS_W1_BASE 0xE67A2100
42#define DBSC3_1_QOS_W2_BASE 0xE67A2200
43#define DBSC3_1_QOS_W3_BASE 0xE67A2300
44#define DBSC3_1_QOS_W4_BASE 0xE67A2400
45#define DBSC3_1_QOS_W5_BASE 0xE67A2500
46#define DBSC3_1_QOS_W6_BASE 0xE67A2600
47#define DBSC3_1_QOS_W7_BASE 0xE67A2700
48#define DBSC3_1_QOS_W8_BASE 0xE67A2800
49#define DBSC3_1_QOS_W9_BASE 0xE67A2900
50#define DBSC3_1_QOS_W10_BASE 0xE67A2A00
51#define DBSC3_1_QOS_W11_BASE 0xE67A2B00
52#define DBSC3_1_QOS_W12_BASE 0xE67A2C00
53#define DBSC3_1_QOS_W13_BASE 0xE67A2D00
54#define DBSC3_1_QOS_W14_BASE 0xE67A2E00
55#define DBSC3_1_QOS_W15_BASE 0xE67A2F00
Nobuhiro Iwamatsu747a3ad2014-05-19 12:23:35 +090056#define DBSC3_1_DBADJ2 0xE67A00C8
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +090057
Nobuhiro Iwamatsu5f4d2802014-12-02 16:52:22 +090058/* Module stop control/status register bits */
59#define MSTP0_BITS 0x00640801
60#define MSTP1_BITS 0x9B6C9B5A
61#define MSTP2_BITS 0x100D21FC
62#define MSTP3_BITS 0xF08CD810
63#define MSTP4_BITS 0x800001C4
64#define MSTP5_BITS 0x44C00046
65#define MSTP7_BITS 0x05BFE618
66#define MSTP8_BITS 0x40C0FE85
67#define MSTP9_BITS 0xFF979FFF
68#define MSTP10_BITS 0xFFFEFFE0
69#define MSTP11_BITS 0x000001C0
70
Nobuhiro Iwamatsudc7ef502014-03-28 13:43:40 +090071#define R8A7791_CUT_ES2X 2
72#define IS_R8A7791_ES2() \
73 (rmobile_get_cpu_rev_integer() == R8A7791_CUT_ES2X)
74
Nobuhiro Iwamatsu4a495bc2013-11-21 17:07:45 +090075#endif /* __ASM_ARCH_R8A7791_H */