Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Michal Simek | 04b7e62 | 2015-01-15 10:01:51 +0100 | [diff] [blame] | 2 | /* |
| 3 | * (C) Copyright 2014 - 2015 Xilinx, Inc. |
| 4 | * Michal Simek <michal.simek@xilinx.com> |
Michal Simek | 04b7e62 | 2015-01-15 10:01:51 +0100 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | #include <common.h> |
Simon Glass | a9dc068 | 2019-12-28 10:44:59 -0700 | [diff] [blame] | 8 | #include <time.h> |
Michal Simek | 0ca5557 | 2015-04-15 14:59:19 +0200 | [diff] [blame] | 9 | #include <asm/arch/clk.h> |
Michal Simek | 04b7e62 | 2015-01-15 10:01:51 +0100 | [diff] [blame] | 10 | #include <asm/arch/hardware.h> |
| 11 | #include <asm/arch/sys_proto.h> |
| 12 | |
| 13 | DECLARE_GLOBAL_DATA_PTR; |
| 14 | |
Michal Simek | c23d3f8 | 2015-11-05 08:34:35 +0100 | [diff] [blame] | 15 | unsigned long zynqmp_get_system_timer_freq(void) |
| 16 | { |
| 17 | u32 ver = zynqmp_get_silicon_version(); |
| 18 | |
| 19 | switch (ver) { |
Michal Simek | c23d3f8 | 2015-11-05 08:34:35 +0100 | [diff] [blame] | 20 | case ZYNQMP_CSU_VERSION_QEMU: |
| 21 | return 50000000; |
| 22 | } |
| 23 | |
| 24 | return 100000000; |
| 25 | } |
| 26 | |
Michal Simek | 04b7e62 | 2015-01-15 10:01:51 +0100 | [diff] [blame] | 27 | #ifdef CONFIG_CLOCKS |
| 28 | /** |
| 29 | * set_cpu_clk_info() - Initialize clock framework |
| 30 | * Always returns zero. |
| 31 | * |
| 32 | * This function is called from common code after relocation and sets up the |
| 33 | * clock framework. The framework must not be used before this function had been |
| 34 | * called. |
| 35 | */ |
| 36 | int set_cpu_clk_info(void) |
| 37 | { |
| 38 | gd->cpu_clk = get_tbclk(); |
| 39 | |
Michal Simek | daf315f | 2018-05-14 15:33:22 +0200 | [diff] [blame] | 40 | gd->bd->bi_arm_freq = gd->cpu_clk / 1000000; |
Michal Simek | 04b7e62 | 2015-01-15 10:01:51 +0100 | [diff] [blame] | 41 | |
| 42 | gd->bd->bi_dsp_freq = 0; |
| 43 | |
| 44 | return 0; |
| 45 | } |
| 46 | #endif |