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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Michal Simek04b7e622015-01-15 10:01:51 +01002/*
3 * (C) Copyright 2014 - 2015 Xilinx, Inc.
4 * Michal Simek <michal.simek@xilinx.com>
Michal Simek04b7e622015-01-15 10:01:51 +01005 */
6
7#include <common.h>
Simon Glassa9dc0682019-12-28 10:44:59 -07008#include <time.h>
Michal Simek0ca55572015-04-15 14:59:19 +02009#include <asm/arch/clk.h>
Michal Simek04b7e622015-01-15 10:01:51 +010010#include <asm/arch/hardware.h>
11#include <asm/arch/sys_proto.h>
12
13DECLARE_GLOBAL_DATA_PTR;
14
Michal Simekc23d3f82015-11-05 08:34:35 +010015unsigned long zynqmp_get_system_timer_freq(void)
16{
17 u32 ver = zynqmp_get_silicon_version();
18
19 switch (ver) {
Michal Simekc23d3f82015-11-05 08:34:35 +010020 case ZYNQMP_CSU_VERSION_QEMU:
21 return 50000000;
22 }
23
24 return 100000000;
25}
26
Michal Simek04b7e622015-01-15 10:01:51 +010027#ifdef CONFIG_CLOCKS
28/**
29 * set_cpu_clk_info() - Initialize clock framework
30 * Always returns zero.
31 *
32 * This function is called from common code after relocation and sets up the
33 * clock framework. The framework must not be used before this function had been
34 * called.
35 */
36int set_cpu_clk_info(void)
37{
38 gd->cpu_clk = get_tbclk();
39
Michal Simekdaf315f2018-05-14 15:33:22 +020040 gd->bd->bi_arm_freq = gd->cpu_clk / 1000000;
Michal Simek04b7e622015-01-15 10:01:51 +010041
42 gd->bd->bi_dsp_freq = 0;
43
44 return 0;
45}
46#endif