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git01.mediatek.com / filogic / uboot / 2d53829778c07140523a0af7e74c22c3b3bb7e33 / . / arch / m68k / include / asm / immap.h
blob: aafa4f40cb35bde075d8d0169c6dfeb8a20b855f [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0+ */
TsiChungLiew2e0aeef2007-07-05 22:39:07 -0500[diff] [blame]2/*
3 * ColdFire Internal Memory Map and Defines
4 *
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]5 * Copyright 2004-2012 Freescale Semiconductor, Inc.
TsiChungLiew2e0aeef2007-07-05 22:39:07 -0500[diff] [blame]6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
TsiChungLiew2e0aeef2007-07-05 22:39:07 -0500[diff] [blame]7 */
8
9#ifndef __IMMAP_H
10#define __IMMAP_H
Stefan Roesef1110122007-07-16 13:11:12 +0200[diff] [blame]11
TsiChung Liewb354aef2009-06-12 11:29:00 +0000[diff] [blame]12#if defined(CONFIG_MCF520x)
13#include <asm/immap_520x.h>
14#include <asm/m520x.h>
15
Tom Rini364d0022023-01-10 11:19:45 -0500[diff] [blame]16#define CFG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x4000))
TsiChung Liewb354aef2009-06-12 11:29:00 +0000[diff] [blame]17
18/* Timer */
Marek Vasut38908f52023-03-23 01:20:39 +0100[diff] [blame]19#if CONFIG_IS_ENABLED(MCFTMR)
Tom Rini364d0022023-01-10 11:19:45 -0500[diff] [blame]20#define CFG_SYS_UDELAY_BASE (MMAP_DTMR0)
21#define CFG_SYS_TMR_BASE (MMAP_DTMR1)
22#define CFG_SYS_TMRPND_REG (((volatile int0_t *)(CFG_SYS_INTR_BASE))->iprh0)
23#define CFG_SYS_TMRINTR_NO (INT0_HI_DTMR1)
24#define CFG_SYS_TMRINTR_MASK (INTC_IPRH_INT33)
25#define CFG_SYS_TMRINTR_PEND (CFG_SYS_TMRINTR_MASK)
26#define CFG_SYS_TMRINTR_PRI (6)
27#define CFG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
Marek Vasut4c77f062023-03-23 01:20:40 +0100[diff] [blame]28#else
29#define CFG_SYS_UDELAY_BASE (MMAP_PIT0)
TsiChung Liewb354aef2009-06-12 11:29:00 +0000[diff] [blame]30#endif
31
Tom Rini364d0022023-01-10 11:19:45 -0500[diff] [blame]32#define CFG_SYS_INTR_BASE (MMAP_INTC0)
33#define CFG_SYS_NUM_IRQS (128)
TsiChung Liewb354aef2009-06-12 11:29:00 +0000[diff] [blame]34#endif /* CONFIG_M520x */
35
TsiChungLiewb859ef12007-08-16 19:23:50 -0500[diff] [blame]36#ifdef CONFIG_M5235
37#include <asm/immap_5235.h>
38#include <asm/m5235.h>
39
Tom Rini364d0022023-01-10 11:19:45 -0500[diff] [blame]40#define CFG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40))
TsiChungLiewb859ef12007-08-16 19:23:50 -0500[diff] [blame]41
42/* Timer */
Marek Vasut38908f52023-03-23 01:20:39 +0100[diff] [blame]43#if CONFIG_IS_ENABLED(MCFTMR)
Tom Rini364d0022023-01-10 11:19:45 -0500[diff] [blame]44#define CFG_SYS_UDELAY_BASE (MMAP_DTMR0)
45#define CFG_SYS_TMR_BASE (MMAP_DTMR3)
46#define CFG_SYS_TMRPND_REG (((volatile int0_t *)(CFG_SYS_INTR_BASE))->iprl0)
47#define CFG_SYS_TMRINTR_NO (INT0_LO_DTMR3)
48#define CFG_SYS_TMRINTR_MASK (INTC_IPRL_INT22)
49#define CFG_SYS_TMRINTR_PEND (CFG_SYS_TMRINTR_MASK)
50#define CFG_SYS_TMRINTR_PRI (0x1E) /* Level must include inorder to work */
51#define CFG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
Marek Vasut4c77f062023-03-23 01:20:40 +0100[diff] [blame]52#else
53#define CFG_SYS_UDELAY_BASE (MMAP_PIT0)
TsiChungLiewb859ef12007-08-16 19:23:50 -0500[diff] [blame]54#endif
55
Tom Rini364d0022023-01-10 11:19:45 -0500[diff] [blame]56#define CFG_SYS_INTR_BASE (MMAP_INTC0)
57#define CFG_SYS_NUM_IRQS (128)
TsiChungLiewb859ef12007-08-16 19:23:50 -0500[diff] [blame]58#endif /* CONFIG_M5235 */
59
TsiChungLiew0e81abc2007-08-15 19:38:15 -0500[diff] [blame]60#ifdef CONFIG_M5249
61#include <asm/immap_5249.h>
62#include <asm/m5249.h>
63
Tom Rini364d0022023-01-10 11:19:45 -0500[diff] [blame]64#define CFG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40))
TsiChungLiew0e81abc2007-08-15 19:38:15 -0500[diff] [blame]65
Tom Rini364d0022023-01-10 11:19:45 -0500[diff] [blame]66#define CFG_SYS_INTR_BASE (MMAP_INTC)
67#define CFG_SYS_NUM_IRQS (64)
TsiChungLiew0e81abc2007-08-15 19:38:15 -0500[diff] [blame]68
69/* Timer */
Marek Vasut38908f52023-03-23 01:20:39 +0100[diff] [blame]70#if CONFIG_IS_ENABLED(MCFTMR)
Tom Rini364d0022023-01-10 11:19:45 -0500[diff] [blame]71#define CFG_SYS_UDELAY_BASE (MMAP_DTMR0)
72#define CFG_SYS_TMR_BASE (MMAP_DTMR1)
73#define CFG_SYS_TMRPND_REG (mbar_readLong(MCFSIM_IPR))
74#define CFG_SYS_TMRINTR_NO (31)
75#define CFG_SYS_TMRINTR_MASK (0x00000400)
76#define CFG_SYS_TMRINTR_PEND (CFG_SYS_TMRINTR_MASK)
77#define CFG_SYS_TMRINTR_PRI (MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3)
78#define CFG_SYS_TIMER_PRESCALER (((gd->bus_clk / 2000000) - 1) << 8)
Marek Vasut4c77f062023-03-23 01:20:40 +0100[diff] [blame]79#else
80#define CFG_SYS_UDELAY_BASE (MMAP_PIT0)
TsiChungLiew0e81abc2007-08-15 19:38:15 -0500[diff] [blame]81#endif
82#endif /* CONFIG_M5249 */
83
TsiChungLiew34674692007-08-16 13:20:50 -0500[diff] [blame]84#ifdef CONFIG_M5253
85#include <asm/immap_5253.h>
86#include <asm/m5249.h>
87#include <asm/m5253.h>
88
Tom Rini364d0022023-01-10 11:19:45 -0500[diff] [blame]89#define CFG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40))
TsiChungLiew34674692007-08-16 13:20:50 -0500[diff] [blame]90
Tom Rini364d0022023-01-10 11:19:45 -0500[diff] [blame]91#define CFG_SYS_INTR_BASE (MMAP_INTC)
92#define CFG_SYS_NUM_IRQS (64)
TsiChungLiew34674692007-08-16 13:20:50 -0500[diff] [blame]93
94/* Timer */
Marek Vasut38908f52023-03-23 01:20:39 +0100[diff] [blame]95#if CONFIG_IS_ENABLED(MCFTMR)
Tom Rini364d0022023-01-10 11:19:45 -0500[diff] [blame]96#define CFG_SYS_UDELAY_BASE (MMAP_DTMR0)
97#define CFG_SYS_TMR_BASE (MMAP_DTMR1)
98#define CFG_SYS_TMRPND_REG (mbar_readLong(MCFSIM_IPR))
99#define CFG_SYS_TMRINTR_NO (27)
100#define CFG_SYS_TMRINTR_MASK (0x00000400)
101#define CFG_SYS_TMRINTR_PEND (CFG_SYS_TMRINTR_MASK)
102#define CFG_SYS_TMRINTR_PRI (MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL3 | MCFSIM_ICR_PRI3)
103#define CFG_SYS_TIMER_PRESCALER (((gd->bus_clk / 2000000) - 1) << 8)
Marek Vasut4c77f062023-03-23 01:20:40 +0100[diff] [blame]104#else
105#define CFG_SYS_UDELAY_BASE (MMAP_PIT0)
TsiChungLiew34674692007-08-16 13:20:50 -0500[diff] [blame]106#endif
107#endif /* CONFIG_M5253 */
108
TsiChungLiew0e81abc2007-08-15 19:38:15 -0500[diff] [blame]109#ifdef CONFIG_M5271
110#include <asm/immap_5271.h>
111#include <asm/m5271.h>
112
Tom Rini364d0022023-01-10 11:19:45 -0500[diff] [blame]113#define CFG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40))
TsiChungLiew0e81abc2007-08-15 19:38:15 -0500[diff] [blame]114
115/* Timer */
Marek Vasut38908f52023-03-23 01:20:39 +0100[diff] [blame]116#if CONFIG_IS_ENABLED(MCFTMR)
Tom Rini364d0022023-01-10 11:19:45 -0500[diff] [blame]117#define CFG_SYS_UDELAY_BASE (MMAP_DTMR0)
118#define CFG_SYS_TMR_BASE (MMAP_DTMR3)
119#define CFG_SYS_TMRPND_REG (((volatile int0_t *)(CFG_SYS_INTR_BASE))->iprl0)
120#define CFG_SYS_TMRINTR_NO (INT0_LO_DTMR3)
121#define CFG_SYS_TMRINTR_MASK (INTC_IPRL_INT22)
122#define CFG_SYS_TMRINTR_PEND (CFG_SYS_TMRINTR_MASK)
123#define CFG_SYS_TMRINTR_PRI (0x1E) /* Interrupt level 3, priority 6 */
124#define CFG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
Marek Vasut4c77f062023-03-23 01:20:40 +0100[diff] [blame]125#else
126#define CFG_SYS_UDELAY_BASE (MMAP_PIT0)
TsiChungLiew0e81abc2007-08-15 19:38:15 -0500[diff] [blame]127#endif
128
Tom Rini364d0022023-01-10 11:19:45 -0500[diff] [blame]129#define CFG_SYS_INTR_BASE (MMAP_INTC0)
130#define CFG_SYS_NUM_IRQS (128)
TsiChungLiew0e81abc2007-08-15 19:38:15 -0500[diff] [blame]131#endif /* CONFIG_M5271 */
132
133#ifdef CONFIG_M5272
134#include <asm/immap_5272.h>
135#include <asm/m5272.h>
136
Tom Rini364d0022023-01-10 11:19:45 -0500[diff] [blame]137#define CFG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40))
TsiChungLiew0e81abc2007-08-15 19:38:15 -0500[diff] [blame]138
Tom Rini364d0022023-01-10 11:19:45 -0500[diff] [blame]139#define CFG_SYS_INTR_BASE (MMAP_INTC)
140#define CFG_SYS_NUM_IRQS (64)
TsiChungLiew0e81abc2007-08-15 19:38:15 -0500[diff] [blame]141
142/* Timer */
Marek Vasut38908f52023-03-23 01:20:39 +0100[diff] [blame]143#if CONFIG_IS_ENABLED(MCFTMR)
Tom Rini364d0022023-01-10 11:19:45 -0500[diff] [blame]144#define CFG_SYS_UDELAY_BASE (MMAP_TMR0)
145#define CFG_SYS_TMR_BASE (MMAP_TMR3)
146#define CFG_SYS_TMRPND_REG (((volatile intctrl_t *)(CFG_SYS_INTR_BASE))->int_isr)
147#define CFG_SYS_TMRINTR_NO (INT_TMR3)
148#define CFG_SYS_TMRINTR_MASK (INT_ISR_INT24)
149#define CFG_SYS_TMRINTR_PEND (0)
150#define CFG_SYS_TMRINTR_PRI (INT_ICR1_TMR3PI | INT_ICR1_TMR3IPL(5))
151#define CFG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
Marek Vasut4c77f062023-03-23 01:20:40 +0100[diff] [blame]152#else
153#define CFG_SYS_UDELAY_BASE (MMAP_PIT0)
TsiChungLiew0e81abc2007-08-15 19:38:15 -0500[diff] [blame]154#endif
155#endif /* CONFIG_M5272 */
156
Matthew Fettke761e2e92008-02-04 15:38:20 -0600[diff] [blame]157#ifdef CONFIG_M5275
158#include <asm/immap_5275.h>
159#include <asm/m5275.h>
160
Tom Rini364d0022023-01-10 11:19:45 -0500[diff] [blame]161#define CFG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40))
Matthew Fettke761e2e92008-02-04 15:38:20 -0600[diff] [blame]162
Tom Rini364d0022023-01-10 11:19:45 -0500[diff] [blame]163#define CFG_SYS_INTR_BASE (MMAP_INTC0)
164#define CFG_SYS_NUM_IRQS (192)
Matthew Fettke761e2e92008-02-04 15:38:20 -0600[diff] [blame]165
166/* Timer */
Marek Vasut38908f52023-03-23 01:20:39 +0100[diff] [blame]167#if CONFIG_IS_ENABLED(MCFTMR)
Tom Rini364d0022023-01-10 11:19:45 -0500[diff] [blame]168#define CFG_SYS_UDELAY_BASE (MMAP_DTMR0)
169#define CFG_SYS_TMR_BASE (MMAP_DTMR3)
170#define CFG_SYS_TMRPND_REG (((volatile int0_t *)(CFG_SYS_INTR_BASE))->iprl0)
171#define CFG_SYS_TMRINTR_NO (INT0_LO_DTMR3)
172#define CFG_SYS_TMRINTR_MASK (INTC_IPRL_INT22)
173#define CFG_SYS_TMRINTR_PEND (CFG_SYS_TMRINTR_MASK)
174#define CFG_SYS_TMRINTR_PRI (0x1E)
175#define CFG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
Marek Vasut4c77f062023-03-23 01:20:40 +0100[diff] [blame]176#else
177#define CFG_SYS_UDELAY_BASE (MMAP_PIT0)
Matthew Fettke761e2e92008-02-04 15:38:20 -0600[diff] [blame]178#endif
179#endif /* CONFIG_M5275 */
180
TsiChungLiew0e81abc2007-08-15 19:38:15 -0500[diff] [blame]181#ifdef CONFIG_M5282
182#include <asm/immap_5282.h>
183#include <asm/m5282.h>
184
Tom Rini364d0022023-01-10 11:19:45 -0500[diff] [blame]185#define CFG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40))
TsiChungLiew0e81abc2007-08-15 19:38:15 -0500[diff] [blame]186
Tom Rini364d0022023-01-10 11:19:45 -0500[diff] [blame]187#define CFG_SYS_INTR_BASE (MMAP_INTC0)
188#define CFG_SYS_NUM_IRQS (128)
TsiChungLiew0e81abc2007-08-15 19:38:15 -0500[diff] [blame]189
190/* Timer */
Marek Vasut38908f52023-03-23 01:20:39 +0100[diff] [blame]191#if CONFIG_IS_ENABLED(MCFTMR)
Tom Rini364d0022023-01-10 11:19:45 -0500[diff] [blame]192#define CFG_SYS_UDELAY_BASE (MMAP_DTMR0)
193#define CFG_SYS_TMR_BASE (MMAP_DTMR3)
194#define CFG_SYS_TMRPND_REG (((volatile int0_t *)(CFG_SYS_INTR_BASE))->iprl0)
195#define CFG_SYS_TMRINTR_NO (INT0_LO_DTMR3)
196#define CFG_SYS_TMRINTR_MASK (1 << INT0_LO_DTMR3)
197#define CFG_SYS_TMRINTR_PEND (CFG_SYS_TMRINTR_MASK)
198#define CFG_SYS_TMRINTR_PRI (0x1E) /* Level must include inorder to work */
199#define CFG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
Marek Vasut4c77f062023-03-23 01:20:40 +0100[diff] [blame]200#else
201#define CFG_SYS_UDELAY_BASE (MMAP_PIT0)
TsiChungLiew0e81abc2007-08-15 19:38:15 -0500[diff] [blame]202#endif
203#endif /* CONFIG_M5282 */
204
angelo@sysam.itbb4ba2c2015-02-12 01:40:00 +0100[diff] [blame]205#ifdef CONFIG_M5307
206#include <asm/immap_5307.h>
207#include <asm/m5307.h>
208
Tom Rini364d0022023-01-10 11:19:45 -0500[diff] [blame]209#define CFG_SYS_UART_BASE (MMAP_UART0 + \
Tom Rini6a5dccc2022-11-16 13:10:41 -0500[diff] [blame]210 (CFG_SYS_UART_PORT * 0x40))
Tom Rini364d0022023-01-10 11:19:45 -0500[diff] [blame]211#define CFG_SYS_INTR_BASE (MMAP_INTC)
212#define CFG_SYS_NUM_IRQS (64)
angelo@sysam.itbb4ba2c2015-02-12 01:40:00 +0100[diff] [blame]213
214/* Timer */
Marek Vasut38908f52023-03-23 01:20:39 +0100[diff] [blame]215#if CONFIG_IS_ENABLED(MCFTMR)
Tom Rini364d0022023-01-10 11:19:45 -0500[diff] [blame]216#define CFG_SYS_UDELAY_BASE (MMAP_DTMR0)
217#define CFG_SYS_TMR_BASE (MMAP_DTMR1)
218#define CFG_SYS_TMRPND_REG (((volatile intctrl_t *) \
219 (CFG_SYS_INTR_BASE))->ipr)
220#define CFG_SYS_TMRINTR_NO (31)
221#define CFG_SYS_TMRINTR_MASK (0x00000400)
222#define CFG_SYS_TMRINTR_PEND (CFG_SYS_TMRINTR_MASK)
223#define CFG_SYS_TMRINTR_PRI (MCFSIM_ICR_AUTOVEC | \
angelo@sysam.itbb4ba2c2015-02-12 01:40:00 +0100[diff] [blame]224 MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3)
Tom Rini364d0022023-01-10 11:19:45 -0500[diff] [blame]225#define CFG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
Marek Vasut4c77f062023-03-23 01:20:40 +0100[diff] [blame]226#else
227#define CFG_SYS_UDELAY_BASE (MMAP_PIT0)
angelo@sysam.itbb4ba2c2015-02-12 01:40:00 +0100[diff] [blame]228#endif
229#endif /* CONFIG_M5307 */
230
TsiChung Liewe7e4fc82008-10-22 11:38:21 +0000[diff] [blame]231#if defined(CONFIG_MCF5301x)
232#include <asm/immap_5301x.h>
233#include <asm/m5301x.h>
234
Tom Rini364d0022023-01-10 11:19:45 -0500[diff] [blame]235#define CFG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x4000))
TsiChung Liewe7e4fc82008-10-22 11:38:21 +0000[diff] [blame]236
TsiChung Liewe7e4fc82008-10-22 11:38:21 +0000[diff] [blame]237/* Timer */
Marek Vasut38908f52023-03-23 01:20:39 +0100[diff] [blame]238#if CONFIG_IS_ENABLED(MCFTMR)
Tom Rini364d0022023-01-10 11:19:45 -0500[diff] [blame]239#define CFG_SYS_UDELAY_BASE (MMAP_DTMR0)
240#define CFG_SYS_TMR_BASE (MMAP_DTMR1)
241#define CFG_SYS_TMRPND_REG (((volatile int0_t *)(CFG_SYS_INTR_BASE))->iprh0)
242#define CFG_SYS_TMRINTR_NO (INT0_HI_DTMR1)
243#define CFG_SYS_TMRINTR_MASK (INTC_IPRH_INT33)
244#define CFG_SYS_TMRINTR_PEND (CFG_SYS_TMRINTR_MASK)
245#define CFG_SYS_TMRINTR_PRI (6)
246#define CFG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
Marek Vasut4c77f062023-03-23 01:20:40 +0100[diff] [blame]247#else
248#define CFG_SYS_UDELAY_BASE (MMAP_PIT0)
TsiChung Liewe7e4fc82008-10-22 11:38:21 +0000[diff] [blame]249#endif
250
Tom Rini364d0022023-01-10 11:19:45 -0500[diff] [blame]251#define CFG_SYS_INTR_BASE (MMAP_INTC0)
252#define CFG_SYS_NUM_IRQS (128)
TsiChung Liewe7e4fc82008-10-22 11:38:21 +0000[diff] [blame]253#endif /* CONFIG_M5301x */
254
TsiChungLiew6f8a0a32008-01-14 17:23:08 -0600[diff] [blame]255#if defined(CONFIG_M5329) || defined(CONFIG_M5373)
TsiChungLiew2e0aeef2007-07-05 22:39:07 -0500[diff] [blame]256#include <asm/immap_5329.h>
257#include <asm/m5329.h>
258
Tom Rini364d0022023-01-10 11:19:45 -0500[diff] [blame]259#define CFG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x4000))
TsiChungLiew2e0aeef2007-07-05 22:39:07 -0500[diff] [blame]260
261/* Timer */
Marek Vasut38908f52023-03-23 01:20:39 +0100[diff] [blame]262#if CONFIG_IS_ENABLED(MCFTMR)
Tom Rini364d0022023-01-10 11:19:45 -0500[diff] [blame]263#define CFG_SYS_UDELAY_BASE (MMAP_DTMR0)
264#define CFG_SYS_TMR_BASE (MMAP_DTMR1)
265#define CFG_SYS_TMRPND_REG (((volatile int0_t *)(CFG_SYS_INTR_BASE))->iprh0)
266#define CFG_SYS_TMRINTR_NO (INT0_HI_DTMR1)
267#define CFG_SYS_TMRINTR_MASK (INTC_IPRH_INT33)
268#define CFG_SYS_TMRINTR_PEND (CFG_SYS_TMRINTR_MASK)
269#define CFG_SYS_TMRINTR_PRI (6)
270#define CFG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
Marek Vasut4c77f062023-03-23 01:20:40 +0100[diff] [blame]271#else
272#define CFG_SYS_UDELAY_BASE (MMAP_PIT0)
TsiChungLiew2e0aeef2007-07-05 22:39:07 -0500[diff] [blame]273#endif
274
Tom Rini364d0022023-01-10 11:19:45 -0500[diff] [blame]275#define CFG_SYS_INTR_BASE (MMAP_INTC0)
276#define CFG_SYS_NUM_IRQS (128)
TsiChungLiew6f8a0a32008-01-14 17:23:08 -0600[diff] [blame]277#endif /* CONFIG_M5329 && CONFIG_M5373 */
Stefan Roesef1110122007-07-16 13:11:12 +0200[diff] [blame]278
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]279#if defined(CONFIG_M54418)
280#include <asm/immap_5441x.h>
281#include <asm/m5441x.h>
282
Tom Rini6a5dccc2022-11-16 13:10:41 -0500[diff] [blame]283#if (CFG_SYS_UART_PORT < 4)
Tom Rini364d0022023-01-10 11:19:45 -0500[diff] [blame]284#define CFG_SYS_UART_BASE (MMAP_UART0 + \
Tom Rini6a5dccc2022-11-16 13:10:41 -0500[diff] [blame]285 (CFG_SYS_UART_PORT * 0x4000))
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]286#else
Tom Rini364d0022023-01-10 11:19:45 -0500[diff] [blame]287#define CFG_SYS_UART_BASE (MMAP_UART4 + \
Tom Rini6a5dccc2022-11-16 13:10:41 -0500[diff] [blame]288 ((CFG_SYS_UART_PORT - 4) * 0x4000))
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]289#endif
290
291#define MMAP_DSPI MMAP_DSPI0
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]292
293/* Timer */
Marek Vasut38908f52023-03-23 01:20:39 +0100[diff] [blame]294#if CONFIG_IS_ENABLED(MCFTMR)
Tom Rini364d0022023-01-10 11:19:45 -0500[diff] [blame]295#define CFG_SYS_UDELAY_BASE (MMAP_DTMR0)
296#define CFG_SYS_TMR_BASE (MMAP_DTMR1)
297#define CFG_SYS_TMRPND_REG (((int0_t *)(CFG_SYS_INTR_BASE))->iprh0)
298#define CFG_SYS_TMRINTR_NO (INT0_HI_DTMR1)
299#define CFG_SYS_TMRINTR_MASK (INTC_IPRH_INT33)
300#define CFG_SYS_TMRINTR_PEND (CFG_SYS_TMRINTR_MASK)
301#define CFG_SYS_TMRINTR_PRI (6)
302#define CFG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
Marek Vasut4c77f062023-03-23 01:20:40 +0100[diff] [blame]303#else
304#define CFG_SYS_UDELAY_BASE (MMAP_PIT0)
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]305#endif
306
Tom Rini364d0022023-01-10 11:19:45 -0500[diff] [blame]307#define CFG_SYS_INTR_BASE (MMAP_INTC0)
308#define CFG_SYS_NUM_IRQS (192)
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]309
310#endif /* CONFIG_M54418 */
311
TsiChungLiew471b2c62008-01-15 13:39:44 -0600[diff] [blame]312#ifdef CONFIG_M547x
313#include <asm/immap_547x_8x.h>
314#include <asm/m547x_8x.h>
315
316#ifdef CONFIG_FSLDMAFEC
TsiChungLiew471b2c62008-01-15 13:39:44 -0600[diff] [blame]317#define FEC0_RX_TASK 0
318#define FEC0_TX_TASK 1
319#define FEC0_RX_PRIORITY 6
320#define FEC0_TX_PRIORITY 7
321#define FEC0_RX_INIT 16
322#define FEC0_TX_INIT 17
323#define FEC1_RX_TASK 2
324#define FEC1_TX_TASK 3
325#define FEC1_RX_PRIORITY 6
326#define FEC1_TX_PRIORITY 7
327#define FEC1_RX_INIT 30
328#define FEC1_TX_INIT 31
329#endif
330
Tom Rini364d0022023-01-10 11:19:45 -0500[diff] [blame]331#define CFG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x100))
TsiChungLiew471b2c62008-01-15 13:39:44 -0600[diff] [blame]332
333#ifdef CONFIG_SLTTMR
Tom Rini364d0022023-01-10 11:19:45 -0500[diff] [blame]334#define CFG_SYS_UDELAY_BASE (MMAP_SLT1)
335#define CFG_SYS_TMR_BASE (MMAP_SLT0)
336#define CFG_SYS_TMRPND_REG (((volatile int0_t *)(CFG_SYS_INTR_BASE))->iprh0)
337#define CFG_SYS_TMRINTR_NO (INT0_HI_SLT0)
338#define CFG_SYS_TMRINTR_MASK (INTC_IPRH_INT54)
339#define CFG_SYS_TMRINTR_PEND (CFG_SYS_TMRINTR_MASK)
340#define CFG_SYS_TMRINTR_PRI (0x1E)
341#define CFG_SYS_TIMER_PRESCALER (gd->bus_clk / 1000000)
TsiChungLiew471b2c62008-01-15 13:39:44 -0600[diff] [blame]342#endif
343
Tom Rini364d0022023-01-10 11:19:45 -0500[diff] [blame]344#define CFG_SYS_INTR_BASE (MMAP_INTC0)
345#define CFG_SYS_NUM_IRQS (128)
TsiChungLiew471b2c62008-01-15 13:39:44 -0600[diff] [blame]346
347#ifdef CONFIG_PCI
Tom Rini56af6592022-11-16 13:10:33 -0500[diff] [blame]348#define CFG_SYS_PCI_BAR0 (0x40000000)
Tom Rinibb4dd962022-11-16 13:10:37 -0500[diff] [blame]349#define CFG_SYS_PCI_BAR1 (CFG_SYS_SDRAM_BASE)
Tom Rini6a5dccc2022-11-16 13:10:41 -0500[diff] [blame]350#define CFG_SYS_PCI_TBATR0 (CFG_SYS_MBAR)
Tom Rinibb4dd962022-11-16 13:10:37 -0500[diff] [blame]351#define CFG_SYS_PCI_TBATR1 (CFG_SYS_SDRAM_BASE)
TsiChungLiew471b2c62008-01-15 13:39:44 -0600[diff] [blame]352#endif
353#endif /* CONFIG_M547x */
354
TsiChungLiew2e0aeef2007-07-05 22:39:07 -0500[diff] [blame]355#endif /* __IMMAP_H */