| Tianling Shen | c900ba8 | 2023-05-30 15:11:21 +0800 | [diff] [blame] | 1 | CONFIG_ARM=y |
| 2 | CONFIG_SKIP_LOWLEVEL_INIT=y |
| 3 | CONFIG_COUNTER_FREQUENCY=24000000 |
| 4 | CONFIG_ARCH_ROCKCHIP=y |
| 5 | CONFIG_TEXT_BASE=0x00a00000 |
| 6 | CONFIG_SPL_LIBCOMMON_SUPPORT=y |
| 7 | CONFIG_SPL_LIBGENERIC_SUPPORT=y |
| 8 | CONFIG_NR_DRAM_BANKS=2 |
| 9 | CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y |
| 10 | CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000 |
| 11 | CONFIG_DEFAULT_DEVICE_TREE="rk3568-nanopi-r5s" |
| 12 | CONFIG_ROCKCHIP_RK3568=y |
| 13 | CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y |
| 14 | CONFIG_SPL_SERIAL=y |
| 15 | CONFIG_SPL_STACK_R_ADDR=0x600000 |
| Tianling Shen | c900ba8 | 2023-05-30 15:11:21 +0800 | [diff] [blame] | 16 | CONFIG_SPL_STACK=0x400000 |
| 17 | CONFIG_DEBUG_UART_BASE=0xFE660000 |
| 18 | CONFIG_DEBUG_UART_CLOCK=24000000 |
| 19 | CONFIG_SYS_LOAD_ADDR=0xc00800 |
| 20 | CONFIG_DEBUG_UART=y |
| 21 | CONFIG_FIT=y |
| 22 | CONFIG_FIT_VERBOSE=y |
| 23 | CONFIG_SPL_LOAD_FIT=y |
| 24 | CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-nanopi-r5s.dtb" |
| 25 | # CONFIG_DISPLAY_CPUINFO is not set |
| 26 | CONFIG_DISPLAY_BOARDINFO_LATE=y |
| 27 | CONFIG_SPL_MAX_SIZE=0x40000 |
| 28 | CONFIG_SPL_PAD_TO=0x7f8000 |
| 29 | CONFIG_SPL_HAS_BSS_LINKER_SECTION=y |
| 30 | CONFIG_SPL_BSS_START_ADDR=0x4000000 |
| 31 | CONFIG_SPL_BSS_MAX_SIZE=0x4000 |
| 32 | # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set |
| 33 | # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set |
| 34 | CONFIG_SPL_STACK_R=y |
| 35 | CONFIG_SPL_ATF=y |
| 36 | CONFIG_CMD_GPIO=y |
| 37 | CONFIG_CMD_GPT=y |
| 38 | CONFIG_CMD_I2C=y |
| 39 | CONFIG_CMD_MMC=y |
| 40 | CONFIG_CMD_USB=y |
| 41 | CONFIG_CMD_PMIC=y |
| 42 | CONFIG_CMD_REGULATOR=y |
| 43 | # CONFIG_SPL_DOS_PARTITION is not set |
| 44 | CONFIG_SPL_OF_CONTROL=y |
| 45 | CONFIG_OF_LIVE=y |
| 46 | CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" |
| 47 | CONFIG_SPL_DM_WARN=y |
| 48 | CONFIG_SPL_REGMAP=y |
| 49 | CONFIG_SPL_SYSCON=y |
| 50 | CONFIG_SPL_CLK=y |
| 51 | CONFIG_ROCKCHIP_GPIO=y |
| 52 | CONFIG_SYS_I2C_ROCKCHIP=y |
| 53 | CONFIG_MISC=y |
| 54 | CONFIG_SUPPORT_EMMC_RPMB=y |
| 55 | CONFIG_MMC_DW=y |
| 56 | CONFIG_MMC_DW_ROCKCHIP=y |
| 57 | CONFIG_MMC_SDHCI=y |
| 58 | CONFIG_MMC_SDHCI_SDMA=y |
| 59 | CONFIG_MMC_SDHCI_ROCKCHIP=y |
| 60 | CONFIG_ETH_DESIGNWARE=y |
| 61 | CONFIG_GMAC_ROCKCHIP=y |
| 62 | CONFIG_PHY_ROCKCHIP_INNO_USB2=y |
| 63 | CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y |
| 64 | CONFIG_POWER_DOMAIN=y |
| 65 | CONFIG_DM_PMIC=y |
| 66 | CONFIG_PMIC_RK8XX=y |
| 67 | CONFIG_SPL_DM_REGULATOR_FIXED=y |
| 68 | CONFIG_REGULATOR_RK8XX=y |
| 69 | CONFIG_PWM_ROCKCHIP=y |
| 70 | CONFIG_SPL_RAM=y |
| 71 | CONFIG_BAUDRATE=1500000 |
| 72 | CONFIG_DEBUG_UART_SHIFT=2 |
| 73 | CONFIG_SYS_NS16550_MEM32=y |
| 74 | CONFIG_SYSRESET=y |
| 75 | CONFIG_SYSRESET_PSCI=y |
| 76 | CONFIG_USB=y |
| 77 | CONFIG_USB_XHCI_HCD=y |
| Tianling Shen | c900ba8 | 2023-05-30 15:11:21 +0800 | [diff] [blame] | 78 | CONFIG_USB_EHCI_HCD=y |
| 79 | CONFIG_USB_EHCI_GENERIC=y |
| 80 | CONFIG_USB_OHCI_HCD=y |
| 81 | CONFIG_USB_OHCI_GENERIC=y |
| 82 | CONFIG_USB_DWC3=y |
| Jonas Karlman | d0de5dc | 2023-07-30 22:59:59 +0000 | [diff] [blame] | 83 | CONFIG_USB_DWC3_GENERIC=y |
| Tianling Shen | c900ba8 | 2023-05-30 15:11:21 +0800 | [diff] [blame] | 84 | CONFIG_ERRNO_STR=y |