blob: 27d0b6a370862ab2a03ddb80d13dd63182069a88 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0 */
Ley Foon Tanb149f2b2017-04-26 02:44:36 +08002/*
3 * Copyright (C) 2016-2017 Intel Corporation
Ley Foon Tanb149f2b2017-04-26 02:44:36 +08004 */
5
6#ifndef _MISC_H_
7#define _MISC_H_
8
Simon Goldschmidtda13a0a2018-10-10 14:55:23 +02009#include <asm/sections.h>
10
Ley Foon Tanb149f2b2017-04-26 02:44:36 +080011void dwmac_deassert_reset(const unsigned int of_reset_id, const u32 phymode);
12
13struct bsel {
14 const char *mode;
15 const char *name;
16};
17
18extern struct bsel bsel_str[];
19
20#ifdef CONFIG_FPGA
Ang, Chee Hongff14f162018-12-19 18:35:15 -080021void socfpga_fpga_add(void *fpga_desc);
Ley Foon Tanb149f2b2017-04-26 02:44:36 +080022#else
Ang, Chee Hongff14f162018-12-19 18:35:15 -080023inline void socfpga_fpga_add(void *fpga_desc) {}
Ley Foon Tanb149f2b2017-04-26 02:44:36 +080024#endif
25
Simon Goldschmidt8e302032018-08-13 21:34:35 +020026#ifdef CONFIG_TARGET_SOCFPGA_GEN5
27void socfpga_sdram_remap_zero(void);
Simon Goldschmidtda13a0a2018-10-10 14:55:23 +020028static inline bool socfpga_is_booting_from_fpga(void)
29{
30 if ((__image_copy_start >= (char *)SOCFPGA_FPGA_SLAVES_ADDRESS) &&
31 (__image_copy_start < (char *)SOCFPGA_STM_ADDRESS))
32 return true;
33 return false;
34}
Simon Goldschmidt8e302032018-08-13 21:34:35 +020035#endif
36
Marek Vasut8fdb4192018-08-18 19:11:52 +020037#ifdef CONFIG_TARGET_SOCFPGA_ARRIA10
38void socfpga_init_security_policies(void);
39void socfpga_sdram_remap_zero(void);
40#endif
41
Marek Vasut713a8a22019-04-16 22:28:08 +020042void do_bridge_reset(int enable, unsigned int mask);
Marek Vasutb6ba4902019-03-21 23:05:38 +010043void socfpga_pl310_clear(void);
Ley Foon Tan4cc6b582018-05-24 00:17:23 +080044
Ley Foon Tanb149f2b2017-04-26 02:44:36 +080045#endif /* _MISC_H_ */