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git01.mediatek.com / filogic / uboot / 2d01b033c23d722cc5298609f75e3916b4e5d9da / . / arch / arm / dts / zynqmp-a2197-g-revA.dts
blob: c6072b5f42730a2978db2dd886c75af9a31e708c [file] [log] [blame]
Michal Simeke42840b2019-03-27 20:14:19 +0100[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * dts file for Xilinx Versal a2197 RevA System Controller on MGT
4 *
5 * (C) Copyright 2019, Xilinx, Inc.
6 *
7 * Michal Simek <michal.simek@xilinx.com>
8 */
9/dts-v1/;
10
11#include "zynqmp.dtsi"
12#include "zynqmp-clk-ccf.dtsi"
13#include <dt-bindings/gpio/gpio.h>
14
15/ {
16 model = "Versal System Controller on a2197 MGT Char board RevA";
17 compatible = "xlnx,zynqmp-a2197-g-revA", "xlnx,zynqmp-a2197-revA",
18 "xlnx,zynqmp-a2197", "xlnx,zynqmp";
19
20 aliases {
21 ethernet0 = &gem0;
22 gpio0 = &gpio;
23 i2c0 = &i2c0;
24 mmc0 = &sdhci0;
25 rtc0 = &rtc;
26 serial0 = &uart0;
27 serial1 = &dcc;
28 usb0 = &usb0;
29 };
30
31 chosen {
32 bootargs = "earlycon";
33 stdout-path = "serial0:115200n8";
34 xlnx,eeprom = <&eeprom>;
35 };
36
37 memory@0 {
38 device_type = "memory";
39 reg = <0x0 0x0 0x0 0x80000000>;
40 };
41};
42
43&sdhci0 { /* emmc MIO 13-23 16GB */
44 status = "okay";
45 non-removable;
46 disable-wp;
47 bus-width = <8>;
48 xlnx,mio_bank = <0>;
49};
50
51&uart0 { /* uart0 MIO38-39 */
52 status = "okay";
53 u-boot,dm-pre-reloc;
54};
55
56&gem0 { /* eth MDIO 76/77 */
57 status = "okay";
58 phy-handle = <&phy0>;
59 phy-mode = "sgmii";
60 is-internal-pcspma;
61 phy0: phy@0 { /* marwell m88e1512 */
62 reg = <0>;
63 reset-gpios = <&gpio 42 GPIO_ACTIVE_LOW>;
64/* xlnx,phy-type = <PHY_TYPE_SGMII>; */
65 };
66/* phy-names = "...";
67 phys = <&lane0 PHY_TYPE_SGMII ... >
68 Note: lane0 sgmii/lane1 usb3 */
69};
70
71&gpio {
72 status = "okay";
73 gpio-line-names = "", "", "", "", "", /* 0 - 4 */
74 "", "", "", "", "", /* 5 - 9 */
75 "", "", "", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */
76 "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */
77 "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */
78 "", "", "", "", "", /* 25 - 29 */
79 "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */
80 "LP_I2C0_PMC_SDA", "", "", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */
81 "", "", "ETH_RESET_B", "", "", /* 40 - 44 */
82 "", "", "", "", "", /* 45 - 49 */
83 "", "", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */
84 "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */
85 "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "", /* 60 - 64 */
86 "", "", "", "", "", /* 65 - 69 */
87 "", "", "", "", "", /* 70 - 74 */
88 "", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */
89 "SYSCTLR_VERSAL_MODE0", "SYSCTLR_VERSAL_MODE1", /* 78 - 79 */
90 "SYSCTLR_VERSAL_MODE2", "SYSCTLR_VERSAL_MODE3", "SYSCTLR_POR_B_LS", "DC_PRSNT", "SYSCTLR_POWER_EN", /* 80 - 84 */
91 "SYSCTLR_JTAG_S0", "SYSCTLR_JTAG_S1", "SYSCTLR_IIC_MUX0_RESET_B", "SYSCTLR_IIC_MUX1_RESET_B", "SYSCTLR_LP_I2C_SM_ALERT", /* 85 -89 */
92 "SYSCTLR_GPIO0", "SYSCTLR_GPIO1", "SYSCTLR_GPIO2", "SYSCTLR_GPIO3", "SYSCTLR_GPIO4", /* 90 - 94 */
93 "SYSCTLR_GPIO5", "VCCO_500_RBIAS", "VCCO_501_RBIAS", "VCCO_502_RBIAS", "VCCO_500_RBIAS_LED", /* 95 - 99 */
94 "VCCO_501_RBIAS_LED", "VCCO_502_RBIAS_LED", "SYSCTLR_VCCINT_EN", "SYSCTLR_VCC_IO_SOC_EN", "SYSCTLR_VCC_PMC_EN", /* 100 - 104 */
95 "SYSCTLR_VCC_RAM_EN", "SYSCTLR_VCC_PSLP_EN", "SYSCTLR_VCC_PSFP_EN", "SYSCTLR_VCCAUX_EN", "SYSCTLR_VCCAUX_PMC_EN", /* 105 - 109 */
96 "SYSCTLR_VCCO_500_EN", "SYSCTLR_VCCO_501_EN", "SYSCTLR_VCCO_502_EN", "SYSCTLR_VCCO_503_EN", "SYSCTLR_VCC1V8_EN", /* 110 - 114 */
97 "SYSCTLR_VCC3V3_EN", "SYSCTLR_VCC1V2_DDR4_EN", "SYSCTLR_VCC1V1_LP4_EN", "SYSCTLR_VDD1_1V8_LP4_EN", "SYSCTLR_VADJ_FMC_EN", /* 115 - 119 */
98 "SYSCTLR_MGTYAVCC_EN", "SYSCTLR_MGTYAVTT_EN", "SYSCTLR_MGTYVCCAUX_EN", "SYSCTLR_UTIL_1V13_EN", "SYSCTLR_UTIL_1V8_EN", /* 120 - 124 */
99 "SYSCTLR_UTIL_2V5_EN", "FMCP1_FMC_PRSNT_M2C_B", "FMCP2_FMC_PRSNT_M2C_B", "FMCP1_FMCP_PRSNT_M2C_B", "FMCP2_FMCP_PRSNT_M2C_B", /* 125 - 129 */
100 "PMBUS1_INA226_ALERT", "PMBUS2_INA226_ALERT", "SYSCTLR_USBC_SBU1", "SYSCTLR_USBC_SBU2", "TI_CABLE1", /* 130 - 134 */
101 "TI_CABLE2", "SYSCTLR_MIC2005_EN_B", "SYSCTLR_MIC2005_FAULT_B", "SYSCTLR_TUSB320_INT_B", "SYSCTLR_TUSB320_ID", /* 135 - 139 */
102 "PMBUS1_ALERT", "PMBUS2_ALERT", "SYSCTLR_ETH_RESET_B", "SYSCTLR_VCC0V85_TG", "MAX6643_OT_B", /* 140 - 144 */
103 "MAX6643_FANFINAL_B", "MAX6643_FULLSPD", "", "", "", /* 145 - 149 */
104 "", "", "", "", "", /* 150 - 154 */
105 "", "", "", "", "", /* 155 - 159 */
106 "", "", "", "", "", /* 160 - 164 */
107 "", "", "", "", "", /* 165 - 169 */
108 "", "", "", ""; /* 170 - 174 */
109};
110
111&i2c0 { /* MIO 34-35 - can't stay here */
112 status = "okay";
113 clock-frequency = <400000>;
114 scl-gpios = <&gpio 34 GPIO_ACTIVE_HIGH>;
115 sda-gpios = <&gpio 35 GPIO_ACTIVE_HIGH>;
116 i2c-mux@74 { /* u94 */
117 compatible = "nxp,pca9548";
118 #address-cells = <1>;
119 #size-cells = <0>;
120 reg = <0x74>;
121 /* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */
122 i2c@0 {
123 #address-cells = <1>;
124 #size-cells = <0>;
125 reg = <0>;
126 /* Use for storing information about SC board */
127 eeprom: eeprom@50 { /* u96 - 24LC32A - 256B */
128 compatible = "atmel,24c32";
129 reg = <0x50>;
130 };
131 };
132 i2c@1 { /* CM_I2C_SCL - Samtec */
133 #address-cells = <1>;
134 #size-cells = <0>;
135 reg = <1>;
136 };
137 i2c@2 { /* PMBUS - AFX_PMBUS */
138 #address-cells = <1>;
139 #size-cells = <0>;
140 reg = <2>;
141 tps544@d { /* u85 */
142 compatible = "ti,tps544b25";
143 reg = <0xd>;
144 };
145 tps544@10 { /* u73 */
146 compatible = "ti,tps544b25";
147 reg = <0x10>;
148 };
149 tps544@11 { /* u76 */
150 compatible = "ti,tps544b25";
151 reg = <0x11>;
152 };
153 tps544@12 { /* u77 */
154 compatible = "ti,tps544b25";
155 reg = <0x12>;
156 };
157 tps544@13 { /* u80 */
158 compatible = "ti,tps544b25";
159 reg = <0x13>;
160 };
161 tps544@14 { /* u81 */
162 compatible = "ti,tps544b25";
163 reg = <0x14>;
164 };
165 tps544@15 { /* u83 */
166 compatible = "ti,tps544b25";
167 reg = <0x15>;
168 };
169 tps544@16 { /* u63 */
170 compatible = "ti,tps544b25";
171 reg = <0x16>;
172 };
173 tps544@17 { /* u66 */
174 compatible = "ti,tps544b25";
175 reg = <0x17>;
176 };
177 tps544@18 { /* u67 */
178 compatible = "ti,tps544b25";
179 reg = <0x18>;
180 };
181 tps544@19 { /* u69 */
182 compatible = "ti,tps544b25";
183 reg = <0x19>;
184 };
185 tps544@1d { /* u88 */
186 compatible = "ti,tps544b25";
187 reg = <0x1d>;
188 };
189 tps544@1e { /* u89 */
190 compatible = "ti,tps544b25";
191 reg = <0x1e>;
192 };
193 tps544@1f { /* u87 */
194 compatible = "ti,tps544b25";
195 reg = <0x1f>;
196 };
197 tps544@20 { /* u71 */
198 compatible = "ti,tps544b25";
199 reg = <0x20>;
200 };
201 ina226@40 { /* u74 */
202 compatible = "ti,ina226";
203 reg = <0x40>;
204 shunt-resistor = <1000>;
205 };
206 ina226@41 { /* u75 */
207 compatible = "ti,ina226";
208 reg = <0x41>;
209 shunt-resistor = <1000>;
210 };
211 ina226@42 { /* u78 */
212 compatible = "ti,ina226";
213 reg = <0x42>;
214 shunt-resistor = <5000>;
215 };
216 ina226@43 { /* u79 */
217 compatible = "ti,ina226";
218 reg = <0x43>;
219 shunt-resistor = <1000>;
220 };
221 ina226@44 { /* u82 */
222 compatible = "ti,ina226";
223 reg = <0x44>;
224 shunt-resistor = <1000>;
225 };
226 ina226@45 { /* u84 */
227 compatible = "ti,ina226";
228 reg = <0x45>;
229 shunt-resistor = <5000>;
230 };
231 tps53681@c0 { /* u53 - FIXME name - don't know what it does - also vcc_io_soc */
232 compatible = "ti,tps53681"; /* FIXME no linux driver */
233 reg = <0xc0>;
234 };
235 };
236 i2c@3 { /* fmc1 via JA2G */
237 #address-cells = <1>;
238 #size-cells = <0>;
239 reg = <3>;
240 eeprom_fmc1: eeprom@50 { /* on FMC */
241 compatible = "atmel,24c04";
242 reg = <0x50>;
243 };
244 };
245 i2c@4 { /* fmc2 via JA3G */
246 #address-cells = <1>;
247 #size-cells = <0>;
248 reg = <4>;
249 eeprom_fmc2: eeprom@50 { /* on FMC */
250 compatible = "atmel,24c04";
251 reg = <0x50>;
252 };
253 };
254 i2c@5 { /* fmc3 via JA4G */
255 #address-cells = <1>;
256 #size-cells = <0>;
257 reg = <5>;
258 eeprom_fmc3: eeprom@50 { /* on FMC */
259 compatible = "atmel,24c04";
260 reg = <0x50>;
261 };
262 };
263 i2c@6 { /* ddr dimm */
264 #address-cells = <1>;
265 #size-cells = <0>;
266 reg = <7>;
267 };
268 /* 7 unused */
269 };
270};
271
272&usb0 { /* USB0 MIO52-63 */
273 status = "okay";
274 xlnx,usb-polarity = <0>;
275 xlnx,usb-reset-mode = <0>;
276};
277
278&dwc3_0 {
279 status = "okay";
280 dr_mode = "peripheral";
281 maximum-speed = "high-speed";
282};