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git01.mediatek.com / filogic / uboot / 2cde1a2ee81156da71c8d89d54bc1efed967534b / . / arch / arm / mach-uniphier / clk / pll-pro4.c
blob: b7dc3e261f81d14d19aacac4f499cc4e67a3eb98 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
Masahiro Yamada9d6652c2016-09-17 03:33:09 +0900[diff] [blame]2/*
3 * Copyright (C) 2013-2014 Panasonic Corporation
4 * Copyright (C) 2015-2016 Socionext Inc.
Masahiro Yamada9d6652c2016-09-17 03:33:09 +0900[diff] [blame]5 */
6
Masahiro Yamadaeb6aeca2017-01-21 18:05:25 +0900[diff] [blame]7#include <linux/delay.h>
Masahiro Yamada9d6652c2016-09-17 03:33:09 +0900[diff] [blame]8#include <linux/io.h>
9
10#include "../init.h"
11#include "../sc-regs.h"
12#include "../sg-regs.h"
13#include "pll.h"
14
15static void vpll_init(void)
16{
17 u32 tmp, clk_mode_axosel;
18
19 /* Set VPLL27A & VPLL27B */
Masahiro Yamada76b31242019-07-10 20:07:40 +0900[diff] [blame]20 tmp = readl(sg_base + SG_PINMON0);
Masahiro Yamada9d6652c2016-09-17 03:33:09 +0900[diff] [blame]21 clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK;
22
23 /* 25MHz or 6.25MHz is default for Pro4R, no need to set VPLLA/B */
24 if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ ||
25 clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_6250KHZ)
26 return;
27
28 /* Disable write protect of VPLL27ACTRL[2-7]*, VPLL27BCTRL[2-8] */
Masahiro Yamadac84024c2019-07-10 20:07:41 +0900[diff] [blame]29 tmp = readl(sc_base + SC_VPLL27ACTRL);
Masahiro Yamada9d6652c2016-09-17 03:33:09 +0900[diff] [blame]30 tmp |= 0x00000001;
Masahiro Yamadac84024c2019-07-10 20:07:41 +0900[diff] [blame]31 writel(tmp, sc_base + SC_VPLL27ACTRL);
32 tmp = readl(sc_base + SC_VPLL27BCTRL);
Masahiro Yamada9d6652c2016-09-17 03:33:09 +0900[diff] [blame]33 tmp |= 0x00000001;
Masahiro Yamadac84024c2019-07-10 20:07:41 +0900[diff] [blame]34 writel(tmp, sc_base + SC_VPLL27BCTRL);
Masahiro Yamada9d6652c2016-09-17 03:33:09 +0900[diff] [blame]35
36 /* Unset VPLA_K_LD and VPLB_K_LD bit */
Masahiro Yamadac84024c2019-07-10 20:07:41 +0900[diff] [blame]37 tmp = readl(sc_base + SC_VPLL27ACTRL3);
Masahiro Yamada9d6652c2016-09-17 03:33:09 +0900[diff] [blame]38 tmp &= ~0x10000000;
Masahiro Yamadac84024c2019-07-10 20:07:41 +0900[diff] [blame]39 writel(tmp, sc_base + SC_VPLL27ACTRL3);
40 tmp = readl(sc_base + SC_VPLL27BCTRL3);
Masahiro Yamada9d6652c2016-09-17 03:33:09 +0900[diff] [blame]41 tmp &= ~0x10000000;
Masahiro Yamadac84024c2019-07-10 20:07:41 +0900[diff] [blame]42 writel(tmp, sc_base + SC_VPLL27BCTRL3);
Masahiro Yamada9d6652c2016-09-17 03:33:09 +0900[diff] [blame]43
44 /* Set VPLA_M and VPLB_M to 0x20 */
Masahiro Yamadac84024c2019-07-10 20:07:41 +0900[diff] [blame]45 tmp = readl(sc_base + SC_VPLL27ACTRL2);
Masahiro Yamada9d6652c2016-09-17 03:33:09 +0900[diff] [blame]46 tmp &= ~0x0000007f;
47 tmp |= 0x00000020;
Masahiro Yamadac84024c2019-07-10 20:07:41 +0900[diff] [blame]48 writel(tmp, sc_base + SC_VPLL27ACTRL2);
49 tmp = readl(sc_base + SC_VPLL27BCTRL2);
Masahiro Yamada9d6652c2016-09-17 03:33:09 +0900[diff] [blame]50 tmp &= ~0x0000007f;
51 tmp |= 0x00000020;
Masahiro Yamadac84024c2019-07-10 20:07:41 +0900[diff] [blame]52 writel(tmp, sc_base + SC_VPLL27BCTRL2);
Masahiro Yamada9d6652c2016-09-17 03:33:09 +0900[diff] [blame]53
54 if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ ||
55 clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_6250KHZ) {
56 /* Set VPLA_K and VPLB_K for AXO: 25MHz */
Masahiro Yamadac84024c2019-07-10 20:07:41 +0900[diff] [blame]57 tmp = readl(sc_base + SC_VPLL27ACTRL3);
Masahiro Yamada9d6652c2016-09-17 03:33:09 +0900[diff] [blame]58 tmp &= ~0x000fffff;
59 tmp |= 0x00066666;
Masahiro Yamadac84024c2019-07-10 20:07:41 +0900[diff] [blame]60 writel(tmp, sc_base + SC_VPLL27ACTRL3);
61 tmp = readl(sc_base + SC_VPLL27BCTRL3);
Masahiro Yamada9d6652c2016-09-17 03:33:09 +0900[diff] [blame]62 tmp &= ~0x000fffff;
63 tmp |= 0x00066666;
Masahiro Yamadac84024c2019-07-10 20:07:41 +0900[diff] [blame]64 writel(tmp, sc_base + SC_VPLL27BCTRL3);
Masahiro Yamada9d6652c2016-09-17 03:33:09 +0900[diff] [blame]65 } else {
66 /* Set VPLA_K and VPLB_K for AXO: 24.576 MHz */
Masahiro Yamadac84024c2019-07-10 20:07:41 +0900[diff] [blame]67 tmp = readl(sc_base + SC_VPLL27ACTRL3);
Masahiro Yamada9d6652c2016-09-17 03:33:09 +0900[diff] [blame]68 tmp &= ~0x000fffff;
69 tmp |= 0x000f5800;
Masahiro Yamadac84024c2019-07-10 20:07:41 +0900[diff] [blame]70 writel(tmp, sc_base + SC_VPLL27ACTRL3);
71 tmp = readl(sc_base + SC_VPLL27BCTRL3);
Masahiro Yamada9d6652c2016-09-17 03:33:09 +0900[diff] [blame]72 tmp &= ~0x000fffff;
73 tmp |= 0x000f5800;
Masahiro Yamadac84024c2019-07-10 20:07:41 +0900[diff] [blame]74 writel(tmp, sc_base + SC_VPLL27BCTRL3);
Masahiro Yamada9d6652c2016-09-17 03:33:09 +0900[diff] [blame]75 }
76
77 /* wait 1 usec */
78 udelay(1);
79
80 /* Set VPLA_K_LD and VPLB_K_LD to load K parameters */
Masahiro Yamadac84024c2019-07-10 20:07:41 +0900[diff] [blame]81 tmp = readl(sc_base + SC_VPLL27ACTRL3);
Masahiro Yamada9d6652c2016-09-17 03:33:09 +0900[diff] [blame]82 tmp |= 0x10000000;
Masahiro Yamadac84024c2019-07-10 20:07:41 +0900[diff] [blame]83 writel(tmp, sc_base + SC_VPLL27ACTRL3);
84 tmp = readl(sc_base + SC_VPLL27BCTRL3);
Masahiro Yamada9d6652c2016-09-17 03:33:09 +0900[diff] [blame]85 tmp |= 0x10000000;
Masahiro Yamadac84024c2019-07-10 20:07:41 +0900[diff] [blame]86 writel(tmp, sc_base + SC_VPLL27BCTRL3);
Masahiro Yamada9d6652c2016-09-17 03:33:09 +0900[diff] [blame]87
88 /* Unset VPLA_SNRST and VPLB_SNRST bit */
Masahiro Yamadac84024c2019-07-10 20:07:41 +0900[diff] [blame]89 tmp = readl(sc_base + SC_VPLL27ACTRL2);
Masahiro Yamada9d6652c2016-09-17 03:33:09 +0900[diff] [blame]90 tmp |= 0x10000000;
Masahiro Yamadac84024c2019-07-10 20:07:41 +0900[diff] [blame]91 writel(tmp, sc_base + SC_VPLL27ACTRL2);
92 tmp = readl(sc_base + SC_VPLL27BCTRL2);
Masahiro Yamada9d6652c2016-09-17 03:33:09 +0900[diff] [blame]93 tmp |= 0x10000000;
Masahiro Yamadac84024c2019-07-10 20:07:41 +0900[diff] [blame]94 writel(tmp, sc_base + SC_VPLL27BCTRL2);
Masahiro Yamada9d6652c2016-09-17 03:33:09 +0900[diff] [blame]95
96 /* Enable write protect of VPLL27ACTRL[2-7]*, VPLL27BCTRL[2-8] */
Masahiro Yamadac84024c2019-07-10 20:07:41 +0900[diff] [blame]97 tmp = readl(sc_base + SC_VPLL27ACTRL);
Masahiro Yamada9d6652c2016-09-17 03:33:09 +0900[diff] [blame]98 tmp &= ~0x00000001;
Masahiro Yamadac84024c2019-07-10 20:07:41 +0900[diff] [blame]99 writel(tmp, sc_base + SC_VPLL27ACTRL);
100 tmp = readl(sc_base + SC_VPLL27BCTRL);
Masahiro Yamada9d6652c2016-09-17 03:33:09 +0900[diff] [blame]101 tmp &= ~0x00000001;
Masahiro Yamadac84024c2019-07-10 20:07:41 +0900[diff] [blame]102 writel(tmp, sc_base + SC_VPLL27BCTRL);
Masahiro Yamada9d6652c2016-09-17 03:33:09 +0900[diff] [blame]103}
104
105void uniphier_pro4_pll_init(void)
106{
107 vpll_init();
108 uniphier_ld4_dpll_ssc_en();
109}