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Tom Rini8b0c8a12018-05-06 18:27:01 -04001/* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */
Patrick Delaunay939d5362018-03-12 10:46:11 +01002/*
3 * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
Patrick Delaunay939d5362018-03-12 10:46:11 +01004 */
5
6#ifndef __MACH_STM32MP_DDR_H_
7#define __MACH_STM32MP_DDR_H_
8
Patrick Delaunay4175f452019-04-10 14:09:26 +02009/* DDR power initializations */
10enum ddr_type {
11 STM32MP_DDR3,
Patrick Delaunay2ebc2112020-03-06 11:14:03 +010012 STM32MP_LPDDR2_16,
13 STM32MP_LPDDR2_32,
14 STM32MP_LPDDR3_16,
15 STM32MP_LPDDR3_32,
Patrick Delaunay4175f452019-04-10 14:09:26 +020016};
17
18int board_ddr_power_init(enum ddr_type ddr_type);
Patrick Delaunay939d5362018-03-12 10:46:11 +010019
20#endif