blob: 760eca40590cd3e69c90ff7d601d6faf758481e7 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Tom Warren85f0ee42011-05-31 10:30:37 +00002/*
3 * (C) Copyright 2009 SAMSUNG Electronics
4 * Minkyu Kang <mk7.kang@samsung.com>
5 * Jaehoon Chung <jh80.chung@samsung.com>
Tom Warren2e86e812019-05-29 09:30:01 -07006 * Portions Copyright 2011-2019 NVIDIA Corporation
Tom Warren85f0ee42011-05-31 10:30:37 +00007 */
8
Stephen Warrenf227e452012-11-06 11:27:30 +00009#include <bouncebuf.h>
Tom Warren85f0ee42011-05-31 10:30:37 +000010#include <common.h>
Simon Glass11c89f32017-05-17 17:18:03 -060011#include <dm.h>
Jaehoon Chung7825d202016-07-19 16:33:36 +090012#include <errno.h>
Simon Glass0f2af882020-05-10 11:40:05 -060013#include <log.h>
Simon Glass9c3b0e42017-07-25 08:30:08 -060014#include <mmc.h>
Stephen Warrenfba87542011-10-31 06:51:36 +000015#include <asm/gpio.h>
Tom Warren85f0ee42011-05-31 10:30:37 +000016#include <asm/io.h>
Tom Warrenab371962012-09-19 15:50:56 -070017#include <asm/arch-tegra/tegra_mmc.h>
Simon Glass4dcacfc2020-05-10 11:40:13 -060018#include <linux/bitops.h>
Simon Glassdbd79542020-05-10 11:40:11 -060019#include <linux/delay.h>
Simon Glassd66c5f72020-02-03 07:36:15 -070020#include <linux/err.h>
Tom Warren2e86e812019-05-29 09:30:01 -070021#if defined(CONFIG_TEGRA30) || defined(CONFIG_TEGRA210)
22#include <asm/arch/clock.h>
23#endif
Tom Warren85f0ee42011-05-31 10:30:37 +000024
Simon Glass8c4c5c82017-04-23 20:02:11 -060025struct tegra_mmc_plat {
26 struct mmc_config cfg;
27 struct mmc mmc;
28};
29
Stephen Warren6d9ccbb2016-09-13 10:45:46 -060030struct tegra_mmc_priv {
31 struct tegra_mmc *reg;
Stephen Warren6d9ccbb2016-09-13 10:45:46 -060032 struct reset_ctl reset_ctl;
33 struct clk clk;
Stephen Warren6d9ccbb2016-09-13 10:45:46 -060034 struct gpio_desc cd_gpio; /* Change Detect GPIO */
35 struct gpio_desc pwr_gpio; /* Power GPIO */
36 struct gpio_desc wp_gpio; /* Write Protect GPIO */
37 unsigned int version; /* SDHCI spec. version */
38 unsigned int clock; /* Current clock (MHz) */
Tom Warren2e86e812019-05-29 09:30:01 -070039 int mmc_id; /* peripheral id */
Stephen Warren6d9ccbb2016-09-13 10:45:46 -060040};
41
Stephen Warren6d9ccbb2016-09-13 10:45:46 -060042static void tegra_mmc_set_power(struct tegra_mmc_priv *priv,
43 unsigned short power)
Tom Warren35ae07b2013-02-26 12:31:26 -070044{
45 u8 pwr = 0;
46 debug("%s: power = %x\n", __func__, power);
47
48 if (power != (unsigned short)-1) {
49 switch (1 << power) {
50 case MMC_VDD_165_195:
51 pwr = TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V1_8;
52 break;
53 case MMC_VDD_29_30:
54 case MMC_VDD_30_31:
55 pwr = TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V3_0;
56 break;
57 case MMC_VDD_32_33:
58 case MMC_VDD_33_34:
59 pwr = TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V3_3;
60 break;
61 }
62 }
63 debug("%s: pwr = %X\n", __func__, pwr);
64
65 /* Set the bus voltage first (if any) */
Stephen Warren6d9ccbb2016-09-13 10:45:46 -060066 writeb(pwr, &priv->reg->pwrcon);
Tom Warren35ae07b2013-02-26 12:31:26 -070067 if (pwr == 0)
68 return;
69
70 /* Now enable bus power */
71 pwr |= TEGRA_MMC_PWRCTL_SD_BUS_POWER;
Stephen Warren6d9ccbb2016-09-13 10:45:46 -060072 writeb(pwr, &priv->reg->pwrcon);
Tom Warren35ae07b2013-02-26 12:31:26 -070073}
74
Stephen Warren6d9ccbb2016-09-13 10:45:46 -060075static void tegra_mmc_prepare_data(struct tegra_mmc_priv *priv,
76 struct mmc_data *data,
77 struct bounce_buffer *bbstate)
Tom Warren85f0ee42011-05-31 10:30:37 +000078{
79 unsigned char ctrl;
80
Tom Warren85f0ee42011-05-31 10:30:37 +000081
Stephen Warrenf227e452012-11-06 11:27:30 +000082 debug("buf: %p (%p), data->blocks: %u, data->blocksize: %u\n",
83 bbstate->bounce_buffer, bbstate->user_buffer, data->blocks,
84 data->blocksize);
85
Stephen Warren6d9ccbb2016-09-13 10:45:46 -060086 writel((u32)(unsigned long)bbstate->bounce_buffer, &priv->reg->sysad);
Tom Warren85f0ee42011-05-31 10:30:37 +000087 /*
88 * DMASEL[4:3]
89 * 00 = Selects SDMA
90 * 01 = Reserved
91 * 10 = Selects 32-bit Address ADMA2
92 * 11 = Selects 64-bit Address ADMA2
93 */
Stephen Warren6d9ccbb2016-09-13 10:45:46 -060094 ctrl = readb(&priv->reg->hostctl);
Anton staaf0dfb31c2011-11-10 11:56:49 +000095 ctrl &= ~TEGRA_MMC_HOSTCTL_DMASEL_MASK;
96 ctrl |= TEGRA_MMC_HOSTCTL_DMASEL_SDMA;
Stephen Warren6d9ccbb2016-09-13 10:45:46 -060097 writeb(ctrl, &priv->reg->hostctl);
Tom Warren85f0ee42011-05-31 10:30:37 +000098
99 /* We do not handle DMA boundaries, so set it to max (512 KiB) */
Stephen Warren6d9ccbb2016-09-13 10:45:46 -0600100 writew((7 << 12) | (data->blocksize & 0xFFF), &priv->reg->blksize);
101 writew(data->blocks, &priv->reg->blkcnt);
Tom Warren85f0ee42011-05-31 10:30:37 +0000102}
103
Stephen Warren6d9ccbb2016-09-13 10:45:46 -0600104static void tegra_mmc_set_transfer_mode(struct tegra_mmc_priv *priv,
105 struct mmc_data *data)
Tom Warren85f0ee42011-05-31 10:30:37 +0000106{
107 unsigned short mode;
108 debug(" mmc_set_transfer_mode called\n");
109 /*
110 * TRNMOD
111 * MUL1SIN0[5] : Multi/Single Block Select
112 * RD1WT0[4] : Data Transfer Direction Select
113 * 1 = read
114 * 0 = write
115 * ENACMD12[2] : Auto CMD12 Enable
116 * ENBLKCNT[1] : Block Count Enable
117 * ENDMA[0] : DMA Enable
118 */
Anton staaf0dfb31c2011-11-10 11:56:49 +0000119 mode = (TEGRA_MMC_TRNMOD_DMA_ENABLE |
120 TEGRA_MMC_TRNMOD_BLOCK_COUNT_ENABLE);
121
Tom Warren85f0ee42011-05-31 10:30:37 +0000122 if (data->blocks > 1)
Anton staaf0dfb31c2011-11-10 11:56:49 +0000123 mode |= TEGRA_MMC_TRNMOD_MULTI_BLOCK_SELECT;
124
Tom Warren85f0ee42011-05-31 10:30:37 +0000125 if (data->flags & MMC_DATA_READ)
Anton staaf0dfb31c2011-11-10 11:56:49 +0000126 mode |= TEGRA_MMC_TRNMOD_DATA_XFER_DIR_SEL_READ;
Tom Warren85f0ee42011-05-31 10:30:37 +0000127
Stephen Warren6d9ccbb2016-09-13 10:45:46 -0600128 writew(mode, &priv->reg->trnmod);
Tom Warren85f0ee42011-05-31 10:30:37 +0000129}
130
Stephen Warren6d9ccbb2016-09-13 10:45:46 -0600131static int tegra_mmc_wait_inhibit(struct tegra_mmc_priv *priv,
132 struct mmc_cmd *cmd,
133 struct mmc_data *data,
134 unsigned int timeout)
Tom Warren85f0ee42011-05-31 10:30:37 +0000135{
Tom Warren85f0ee42011-05-31 10:30:37 +0000136 /*
137 * PRNSTS
Anton staaf5ab3fba2011-11-10 11:56:52 +0000138 * CMDINHDAT[1] : Command Inhibit (DAT)
139 * CMDINHCMD[0] : Command Inhibit (CMD)
Tom Warren85f0ee42011-05-31 10:30:37 +0000140 */
Anton staaf5ab3fba2011-11-10 11:56:52 +0000141 unsigned int mask = TEGRA_MMC_PRNSTS_CMD_INHIBIT_CMD;
Tom Warren85f0ee42011-05-31 10:30:37 +0000142
143 /*
144 * We shouldn't wait for data inhibit for stop commands, even
145 * though they might use busy signaling
146 */
Anton staaf5ab3fba2011-11-10 11:56:52 +0000147 if ((data == NULL) && (cmd->resp_type & MMC_RSP_BUSY))
148 mask |= TEGRA_MMC_PRNSTS_CMD_INHIBIT_DAT;
Tom Warren85f0ee42011-05-31 10:30:37 +0000149
Stephen Warren6d9ccbb2016-09-13 10:45:46 -0600150 while (readl(&priv->reg->prnsts) & mask) {
Tom Warren85f0ee42011-05-31 10:30:37 +0000151 if (timeout == 0) {
152 printf("%s: timeout error\n", __func__);
153 return -1;
154 }
155 timeout--;
156 udelay(1000);
157 }
158
Anton staaf5ab3fba2011-11-10 11:56:52 +0000159 return 0;
160}
161
Simon Glass8c4c5c82017-04-23 20:02:11 -0600162static int tegra_mmc_send_cmd_bounced(struct udevice *dev, struct mmc_cmd *cmd,
Stephen Warren6d9ccbb2016-09-13 10:45:46 -0600163 struct mmc_data *data,
164 struct bounce_buffer *bbstate)
Anton staaf5ab3fba2011-11-10 11:56:52 +0000165{
Simon Glass8c4c5c82017-04-23 20:02:11 -0600166 struct tegra_mmc_priv *priv = dev_get_priv(dev);
Anton staaf5ab3fba2011-11-10 11:56:52 +0000167 int flags, i;
168 int result;
Anatolij Gustschine1f53412012-03-28 03:40:00 +0000169 unsigned int mask = 0;
Anton staaf5ab3fba2011-11-10 11:56:52 +0000170 unsigned int retry = 0x100000;
171 debug(" mmc_send_cmd called\n");
172
Stephen Warren6d9ccbb2016-09-13 10:45:46 -0600173 result = tegra_mmc_wait_inhibit(priv, cmd, data, 10 /* ms */);
Anton staaf5ab3fba2011-11-10 11:56:52 +0000174
175 if (result < 0)
176 return result;
177
Tom Warren85f0ee42011-05-31 10:30:37 +0000178 if (data)
Stephen Warren6d9ccbb2016-09-13 10:45:46 -0600179 tegra_mmc_prepare_data(priv, data, bbstate);
Tom Warren85f0ee42011-05-31 10:30:37 +0000180
181 debug("cmd->arg: %08x\n", cmd->cmdarg);
Stephen Warren6d9ccbb2016-09-13 10:45:46 -0600182 writel(cmd->cmdarg, &priv->reg->argument);
Tom Warren85f0ee42011-05-31 10:30:37 +0000183
184 if (data)
Stephen Warren6d9ccbb2016-09-13 10:45:46 -0600185 tegra_mmc_set_transfer_mode(priv, data);
Tom Warren85f0ee42011-05-31 10:30:37 +0000186
187 if ((cmd->resp_type & MMC_RSP_136) && (cmd->resp_type & MMC_RSP_BUSY))
188 return -1;
189
190 /*
191 * CMDREG
192 * CMDIDX[13:8] : Command index
193 * DATAPRNT[5] : Data Present Select
194 * ENCMDIDX[4] : Command Index Check Enable
195 * ENCMDCRC[3] : Command CRC Check Enable
196 * RSPTYP[1:0]
197 * 00 = No Response
198 * 01 = Length 136
199 * 10 = Length 48
200 * 11 = Length 48 Check busy after response
201 */
202 if (!(cmd->resp_type & MMC_RSP_PRESENT))
Anton staaf0dfb31c2011-11-10 11:56:49 +0000203 flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_NO_RESPONSE;
Tom Warren85f0ee42011-05-31 10:30:37 +0000204 else if (cmd->resp_type & MMC_RSP_136)
Anton staaf0dfb31c2011-11-10 11:56:49 +0000205 flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_136;
Tom Warren85f0ee42011-05-31 10:30:37 +0000206 else if (cmd->resp_type & MMC_RSP_BUSY)
Anton staaf0dfb31c2011-11-10 11:56:49 +0000207 flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_48_BUSY;
Tom Warren85f0ee42011-05-31 10:30:37 +0000208 else
Anton staaf0dfb31c2011-11-10 11:56:49 +0000209 flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_48;
Tom Warren85f0ee42011-05-31 10:30:37 +0000210
211 if (cmd->resp_type & MMC_RSP_CRC)
Anton staaf0dfb31c2011-11-10 11:56:49 +0000212 flags |= TEGRA_MMC_TRNMOD_CMD_CRC_CHECK;
Tom Warren85f0ee42011-05-31 10:30:37 +0000213 if (cmd->resp_type & MMC_RSP_OPCODE)
Anton staaf0dfb31c2011-11-10 11:56:49 +0000214 flags |= TEGRA_MMC_TRNMOD_CMD_INDEX_CHECK;
Tom Warren85f0ee42011-05-31 10:30:37 +0000215 if (data)
Anton staaf0dfb31c2011-11-10 11:56:49 +0000216 flags |= TEGRA_MMC_TRNMOD_DATA_PRESENT_SELECT_DATA_TRANSFER;
Tom Warren85f0ee42011-05-31 10:30:37 +0000217
218 debug("cmd: %d\n", cmd->cmdidx);
219
Stephen Warren6d9ccbb2016-09-13 10:45:46 -0600220 writew((cmd->cmdidx << 8) | flags, &priv->reg->cmdreg);
Tom Warren85f0ee42011-05-31 10:30:37 +0000221
222 for (i = 0; i < retry; i++) {
Stephen Warren6d9ccbb2016-09-13 10:45:46 -0600223 mask = readl(&priv->reg->norintsts);
Tom Warren85f0ee42011-05-31 10:30:37 +0000224 /* Command Complete */
Anton staaf0dfb31c2011-11-10 11:56:49 +0000225 if (mask & TEGRA_MMC_NORINTSTS_CMD_COMPLETE) {
Tom Warren85f0ee42011-05-31 10:30:37 +0000226 if (!data)
Stephen Warren6d9ccbb2016-09-13 10:45:46 -0600227 writel(mask, &priv->reg->norintsts);
Tom Warren85f0ee42011-05-31 10:30:37 +0000228 break;
229 }
230 }
231
232 if (i == retry) {
233 printf("%s: waiting for status update\n", __func__);
Stephen Warren6d9ccbb2016-09-13 10:45:46 -0600234 writel(mask, &priv->reg->norintsts);
Jaehoon Chung7825d202016-07-19 16:33:36 +0900235 return -ETIMEDOUT;
Tom Warren85f0ee42011-05-31 10:30:37 +0000236 }
237
Anton staaf0dfb31c2011-11-10 11:56:49 +0000238 if (mask & TEGRA_MMC_NORINTSTS_CMD_TIMEOUT) {
Tom Warren85f0ee42011-05-31 10:30:37 +0000239 /* Timeout Error */
240 debug("timeout: %08x cmd %d\n", mask, cmd->cmdidx);
Stephen Warren6d9ccbb2016-09-13 10:45:46 -0600241 writel(mask, &priv->reg->norintsts);
Jaehoon Chung7825d202016-07-19 16:33:36 +0900242 return -ETIMEDOUT;
Anton staaf0dfb31c2011-11-10 11:56:49 +0000243 } else if (mask & TEGRA_MMC_NORINTSTS_ERR_INTERRUPT) {
Tom Warren85f0ee42011-05-31 10:30:37 +0000244 /* Error Interrupt */
245 debug("error: %08x cmd %d\n", mask, cmd->cmdidx);
Stephen Warren6d9ccbb2016-09-13 10:45:46 -0600246 writel(mask, &priv->reg->norintsts);
Tom Warren85f0ee42011-05-31 10:30:37 +0000247 return -1;
248 }
249
250 if (cmd->resp_type & MMC_RSP_PRESENT) {
251 if (cmd->resp_type & MMC_RSP_136) {
252 /* CRC is stripped so we need to do some shifting. */
253 for (i = 0; i < 4; i++) {
Stephen Warren6d9ccbb2016-09-13 10:45:46 -0600254 unsigned long offset = (unsigned long)
255 (&priv->reg->rspreg3 - i);
Tom Warren85f0ee42011-05-31 10:30:37 +0000256 cmd->response[i] = readl(offset) << 8;
257
258 if (i != 3) {
259 cmd->response[i] |=
260 readb(offset - 1);
261 }
262 debug("cmd->resp[%d]: %08x\n",
263 i, cmd->response[i]);
264 }
265 } else if (cmd->resp_type & MMC_RSP_BUSY) {
266 for (i = 0; i < retry; i++) {
267 /* PRNTDATA[23:20] : DAT[3:0] Line Signal */
Stephen Warren6d9ccbb2016-09-13 10:45:46 -0600268 if (readl(&priv->reg->prnsts)
Tom Warren85f0ee42011-05-31 10:30:37 +0000269 & (1 << 20)) /* DAT[0] */
270 break;
271 }
272
273 if (i == retry) {
274 printf("%s: card is still busy\n", __func__);
Stephen Warren6d9ccbb2016-09-13 10:45:46 -0600275 writel(mask, &priv->reg->norintsts);
Jaehoon Chung7825d202016-07-19 16:33:36 +0900276 return -ETIMEDOUT;
Tom Warren85f0ee42011-05-31 10:30:37 +0000277 }
278
Stephen Warren6d9ccbb2016-09-13 10:45:46 -0600279 cmd->response[0] = readl(&priv->reg->rspreg0);
Tom Warren85f0ee42011-05-31 10:30:37 +0000280 debug("cmd->resp[0]: %08x\n", cmd->response[0]);
281 } else {
Stephen Warren6d9ccbb2016-09-13 10:45:46 -0600282 cmd->response[0] = readl(&priv->reg->rspreg0);
Tom Warren85f0ee42011-05-31 10:30:37 +0000283 debug("cmd->resp[0]: %08x\n", cmd->response[0]);
284 }
285 }
286
287 if (data) {
Anton staafbd348422011-11-10 11:56:51 +0000288 unsigned long start = get_timer(0);
289
Tom Warren85f0ee42011-05-31 10:30:37 +0000290 while (1) {
Stephen Warren6d9ccbb2016-09-13 10:45:46 -0600291 mask = readl(&priv->reg->norintsts);
Tom Warren85f0ee42011-05-31 10:30:37 +0000292
Anton staaf0dfb31c2011-11-10 11:56:49 +0000293 if (mask & TEGRA_MMC_NORINTSTS_ERR_INTERRUPT) {
Tom Warren85f0ee42011-05-31 10:30:37 +0000294 /* Error Interrupt */
Stephen Warren6d9ccbb2016-09-13 10:45:46 -0600295 writel(mask, &priv->reg->norintsts);
Tom Warren85f0ee42011-05-31 10:30:37 +0000296 printf("%s: error during transfer: 0x%08x\n",
297 __func__, mask);
298 return -1;
Anton staaf0dfb31c2011-11-10 11:56:49 +0000299 } else if (mask & TEGRA_MMC_NORINTSTS_DMA_INTERRUPT) {
Anton staaf3ade2102011-11-10 11:56:50 +0000300 /*
301 * DMA Interrupt, restart the transfer where
302 * it was interrupted.
303 */
Stephen Warren6d9ccbb2016-09-13 10:45:46 -0600304 unsigned int address = readl(&priv->reg->sysad);
Anton staaf3ade2102011-11-10 11:56:50 +0000305
Tom Warren85f0ee42011-05-31 10:30:37 +0000306 debug("DMA end\n");
Anton staaf3ade2102011-11-10 11:56:50 +0000307 writel(TEGRA_MMC_NORINTSTS_DMA_INTERRUPT,
Stephen Warren6d9ccbb2016-09-13 10:45:46 -0600308 &priv->reg->norintsts);
309 writel(address, &priv->reg->sysad);
Anton staaf0dfb31c2011-11-10 11:56:49 +0000310 } else if (mask & TEGRA_MMC_NORINTSTS_XFER_COMPLETE) {
Tom Warren85f0ee42011-05-31 10:30:37 +0000311 /* Transfer Complete */
312 debug("r/w is done\n");
313 break;
Marcel Ziswilere1207e92014-10-04 01:48:53 +0200314 } else if (get_timer(start) > 8000UL) {
Stephen Warren6d9ccbb2016-09-13 10:45:46 -0600315 writel(mask, &priv->reg->norintsts);
Anton staafbd348422011-11-10 11:56:51 +0000316 printf("%s: MMC Timeout\n"
317 " Interrupt status 0x%08x\n"
318 " Interrupt status enable 0x%08x\n"
319 " Interrupt signal enable 0x%08x\n"
320 " Present status 0x%08x\n",
321 __func__, mask,
Stephen Warren6d9ccbb2016-09-13 10:45:46 -0600322 readl(&priv->reg->norintstsen),
323 readl(&priv->reg->norintsigen),
324 readl(&priv->reg->prnsts));
Anton staafbd348422011-11-10 11:56:51 +0000325 return -1;
Tom Warren85f0ee42011-05-31 10:30:37 +0000326 }
327 }
Stephen Warren6d9ccbb2016-09-13 10:45:46 -0600328 writel(mask, &priv->reg->norintsts);
Tom Warren85f0ee42011-05-31 10:30:37 +0000329 }
330
331 udelay(1000);
332 return 0;
333}
334
Simon Glass8c4c5c82017-04-23 20:02:11 -0600335static int tegra_mmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
Stephen Warren6d9ccbb2016-09-13 10:45:46 -0600336 struct mmc_data *data)
Stephen Warrenf227e452012-11-06 11:27:30 +0000337{
338 void *buf;
339 unsigned int bbflags;
340 size_t len;
341 struct bounce_buffer bbstate;
342 int ret;
343
344 if (data) {
345 if (data->flags & MMC_DATA_READ) {
346 buf = data->dest;
347 bbflags = GEN_BB_WRITE;
348 } else {
349 buf = (void *)data->src;
350 bbflags = GEN_BB_READ;
351 }
352 len = data->blocks * data->blocksize;
353
354 bounce_buffer_start(&bbstate, buf, len, bbflags);
355 }
356
Simon Glass8c4c5c82017-04-23 20:02:11 -0600357 ret = tegra_mmc_send_cmd_bounced(dev, cmd, data, &bbstate);
Stephen Warrenf227e452012-11-06 11:27:30 +0000358
359 if (data)
360 bounce_buffer_stop(&bbstate);
361
362 return ret;
363}
364
Stephen Warren6d9ccbb2016-09-13 10:45:46 -0600365static void tegra_mmc_change_clock(struct tegra_mmc_priv *priv, uint clock)
Tom Warren85f0ee42011-05-31 10:30:37 +0000366{
Stephen Warrenf79df4b2016-09-13 10:46:01 -0600367 ulong rate;
Simon Glassc2ea5e42011-09-21 12:40:04 +0000368 int div;
Tom Warren85f0ee42011-05-31 10:30:37 +0000369 unsigned short clk;
370 unsigned long timeout;
Simon Glassc2ea5e42011-09-21 12:40:04 +0000371
Tom Warren85f0ee42011-05-31 10:30:37 +0000372 debug(" mmc_change_clock called\n");
373
Simon Glassc2ea5e42011-09-21 12:40:04 +0000374 /*
Tom Warren35ae07b2013-02-26 12:31:26 -0700375 * Change Tegra SDMMCx clock divisor here. Source is PLLP_OUT0
Simon Glassc2ea5e42011-09-21 12:40:04 +0000376 */
Tom Warren85f0ee42011-05-31 10:30:37 +0000377 if (clock == 0)
378 goto out;
Stephen Warrenf79df4b2016-09-13 10:46:01 -0600379
380 rate = clk_set_rate(&priv->clk, clock);
381 div = (rate + clock - 1) / clock;
Tom Warren4ff710a2019-06-03 16:06:34 -0700382
383#if defined(CONFIG_TEGRA210)
384 if (priv->mmc_id == PERIPH_ID_SDMMC1 && clock <= 400000) {
385 /* clock_adjust_periph_pll_div() chooses a 'bad' clock
386 * on SDMMC1 T210, so skip it here and force a clock
387 * that's been spec'd in the table in the TRM for
388 * card-detect (400KHz).
389 */
390 uint effective_rate = clock_adjust_periph_pll_div(priv->mmc_id,
391 CLOCK_ID_PERIPH, 24727273, NULL);
392 div = 62;
393
394 debug("%s: WAR: Using SDMMC1 clock of %u, div %d to achieve %dHz card clock ...\n",
395 __func__, effective_rate, div, clock);
396 } else {
397 clock_adjust_periph_pll_div(priv->mmc_id, CLOCK_ID_PERIPH,
398 clock, &div);
399 }
400#endif
Simon Glassc2ea5e42011-09-21 12:40:04 +0000401 debug("div = %d\n", div);
Tom Warren85f0ee42011-05-31 10:30:37 +0000402
Stephen Warren6d9ccbb2016-09-13 10:45:46 -0600403 writew(0, &priv->reg->clkcon);
Tom Warren85f0ee42011-05-31 10:30:37 +0000404
Tom Warren85f0ee42011-05-31 10:30:37 +0000405 /*
406 * CLKCON
407 * SELFREQ[15:8] : base clock divided by value
408 * ENSDCLK[2] : SD Clock Enable
409 * STBLINTCLK[1] : Internal Clock Stable
410 * ENINTCLK[0] : Internal Clock Enable
411 */
Simon Glassc2ea5e42011-09-21 12:40:04 +0000412 div >>= 1;
Anton staaf0dfb31c2011-11-10 11:56:49 +0000413 clk = ((div << TEGRA_MMC_CLKCON_SDCLK_FREQ_SEL_SHIFT) |
414 TEGRA_MMC_CLKCON_INTERNAL_CLOCK_ENABLE);
Stephen Warren6d9ccbb2016-09-13 10:45:46 -0600415 writew(clk, &priv->reg->clkcon);
Tom Warren85f0ee42011-05-31 10:30:37 +0000416
417 /* Wait max 10 ms */
418 timeout = 10;
Stephen Warren6d9ccbb2016-09-13 10:45:46 -0600419 while (!(readw(&priv->reg->clkcon) &
Anton staaf0dfb31c2011-11-10 11:56:49 +0000420 TEGRA_MMC_CLKCON_INTERNAL_CLOCK_STABLE)) {
Tom Warren85f0ee42011-05-31 10:30:37 +0000421 if (timeout == 0) {
422 printf("%s: timeout error\n", __func__);
423 return;
424 }
425 timeout--;
426 udelay(1000);
427 }
428
Anton staaf0dfb31c2011-11-10 11:56:49 +0000429 clk |= TEGRA_MMC_CLKCON_SD_CLOCK_ENABLE;
Stephen Warren6d9ccbb2016-09-13 10:45:46 -0600430 writew(clk, &priv->reg->clkcon);
Tom Warren85f0ee42011-05-31 10:30:37 +0000431
432 debug("mmc_change_clock: clkcon = %08X\n", clk);
Tom Warren85f0ee42011-05-31 10:30:37 +0000433
434out:
Stephen Warren6d9ccbb2016-09-13 10:45:46 -0600435 priv->clock = clock;
Tom Warren85f0ee42011-05-31 10:30:37 +0000436}
437
Simon Glass8c4c5c82017-04-23 20:02:11 -0600438static int tegra_mmc_set_ios(struct udevice *dev)
Tom Warren85f0ee42011-05-31 10:30:37 +0000439{
Simon Glass8c4c5c82017-04-23 20:02:11 -0600440 struct tegra_mmc_priv *priv = dev_get_priv(dev);
441 struct mmc *mmc = mmc_get_mmc_dev(dev);
Tom Warren85f0ee42011-05-31 10:30:37 +0000442 unsigned char ctrl;
443 debug(" mmc_set_ios called\n");
444
445 debug("bus_width: %x, clock: %d\n", mmc->bus_width, mmc->clock);
446
447 /* Change clock first */
Stephen Warren6d9ccbb2016-09-13 10:45:46 -0600448 tegra_mmc_change_clock(priv, mmc->clock);
Tom Warren85f0ee42011-05-31 10:30:37 +0000449
Stephen Warren6d9ccbb2016-09-13 10:45:46 -0600450 ctrl = readb(&priv->reg->hostctl);
Tom Warren85f0ee42011-05-31 10:30:37 +0000451
452 /*
453 * WIDE8[5]
454 * 0 = Depend on WIDE4
455 * 1 = 8-bit mode
456 * WIDE4[1]
457 * 1 = 4-bit mode
458 * 0 = 1-bit mode
459 */
460 if (mmc->bus_width == 8)
461 ctrl |= (1 << 5);
462 else if (mmc->bus_width == 4)
463 ctrl |= (1 << 1);
464 else
Simon Glass9d6551a2017-06-07 21:11:48 -0600465 ctrl &= ~(1 << 1 | 1 << 5);
Tom Warren85f0ee42011-05-31 10:30:37 +0000466
Stephen Warren6d9ccbb2016-09-13 10:45:46 -0600467 writeb(ctrl, &priv->reg->hostctl);
Tom Warren85f0ee42011-05-31 10:30:37 +0000468 debug("mmc_set_ios: hostctl = %08X\n", ctrl);
Jaehoon Chungb6cd1d32016-12-30 15:30:16 +0900469
470 return 0;
Tom Warren85f0ee42011-05-31 10:30:37 +0000471}
472
Stephen Warren6d9ccbb2016-09-13 10:45:46 -0600473static void tegra_mmc_pad_init(struct tegra_mmc_priv *priv)
Stephen Warrenc76e9362016-09-13 10:45:44 -0600474{
Tom Warren2e86e812019-05-29 09:30:01 -0700475#if defined(CONFIG_TEGRA30) || defined(CONFIG_TEGRA210)
Stephen Warrenc76e9362016-09-13 10:45:44 -0600476 u32 val;
Tom Warren2e86e812019-05-29 09:30:01 -0700477 u16 clk_con;
478 int timeout;
479 int id = priv->mmc_id;
Stephen Warrenc76e9362016-09-13 10:45:44 -0600480
Tom Warren2e86e812019-05-29 09:30:01 -0700481 debug("%s: sdmmc address = %p, id = %d\n", __func__,
482 priv->reg, id);
Stephen Warrenc76e9362016-09-13 10:45:44 -0600483
484 /* Set the pad drive strength for SDMMC1 or 3 only */
Tom Warren2e86e812019-05-29 09:30:01 -0700485 if (id != PERIPH_ID_SDMMC1 && id != PERIPH_ID_SDMMC3) {
Stephen Warrenc76e9362016-09-13 10:45:44 -0600486 debug("%s: settings are only valid for SDMMC1/SDMMC3!\n",
Tom Warren2e86e812019-05-29 09:30:01 -0700487 __func__);
Stephen Warrenc76e9362016-09-13 10:45:44 -0600488 return;
489 }
490
Stephen Warren6d9ccbb2016-09-13 10:45:46 -0600491 val = readl(&priv->reg->sdmemcmppadctl);
Stephen Warrenc76e9362016-09-13 10:45:44 -0600492 val &= 0xFFFFFFF0;
493 val |= MEMCOMP_PADCTRL_VREF;
Stephen Warren6d9ccbb2016-09-13 10:45:46 -0600494 writel(val, &priv->reg->sdmemcmppadctl);
Stephen Warrenc76e9362016-09-13 10:45:44 -0600495
Tom Warren2e86e812019-05-29 09:30:01 -0700496 /* Disable SD Clock Enable before running auto-cal as per TRM */
497 clk_con = readw(&priv->reg->clkcon);
498 debug("%s: CLOCK_CONTROL = 0x%04X\n", __func__, clk_con);
499 clk_con &= ~TEGRA_MMC_CLKCON_SD_CLOCK_ENABLE;
500 writew(clk_con, &priv->reg->clkcon);
501
Stephen Warren6d9ccbb2016-09-13 10:45:46 -0600502 val = readl(&priv->reg->autocalcfg);
Stephen Warrenc76e9362016-09-13 10:45:44 -0600503 val &= 0xFFFF0000;
Tom Warren2e86e812019-05-29 09:30:01 -0700504 val |= AUTO_CAL_PU_OFFSET | AUTO_CAL_PD_OFFSET;
Stephen Warren6d9ccbb2016-09-13 10:45:46 -0600505 writel(val, &priv->reg->autocalcfg);
Tom Warren2e86e812019-05-29 09:30:01 -0700506 val |= AUTO_CAL_START | AUTO_CAL_ENABLE;
507 writel(val, &priv->reg->autocalcfg);
508 debug("%s: AUTO_CAL_CFG = 0x%08X\n", __func__, val);
509 udelay(1);
510 timeout = 100; /* 10 mSec max (100*100uS) */
511 do {
512 val = readl(&priv->reg->autocalsts);
513 udelay(100);
514 } while ((val & AUTO_CAL_ACTIVE) && --timeout);
515 val = readl(&priv->reg->autocalsts);
516 debug("%s: Final AUTO_CAL_STATUS = 0x%08X, timeout = %d\n",
517 __func__, val, timeout);
518
519 /* Re-enable SD Clock Enable when auto-cal is done */
520 clk_con |= TEGRA_MMC_CLKCON_SD_CLOCK_ENABLE;
521 writew(clk_con, &priv->reg->clkcon);
522 clk_con = readw(&priv->reg->clkcon);
523 debug("%s: final CLOCK_CONTROL = 0x%04X\n", __func__, clk_con);
524
525 if (timeout == 0) {
526 printf("%s: Warning: Autocal timed out!\n", __func__);
527 /* TBD: Set CFG2TMC_SDMMC1_PAD_CAL_DRV* regs here */
528 }
529
530#if defined(CONFIG_TEGRA210)
531 u32 tap_value, trim_value;
532
533 /* Set tap/trim values for SDMMC1/3 @ <48MHz here */
534 val = readl(&priv->reg->venspictl); /* aka VENDOR_SYS_SW_CNTL */
535 val &= IO_TRIM_BYPASS_MASK;
536 if (id == PERIPH_ID_SDMMC1) {
537 tap_value = 4; /* default */
538 if (val)
539 tap_value = 3;
540 trim_value = 2;
541 } else { /* SDMMC3 */
542 tap_value = 3;
543 trim_value = 3;
544 }
545
546 val = readl(&priv->reg->venclkctl);
547 val &= ~TRIM_VAL_MASK;
548 val |= (trim_value << TRIM_VAL_SHIFT);
549 val &= ~TAP_VAL_MASK;
550 val |= (tap_value << TAP_VAL_SHIFT);
551 writel(val, &priv->reg->venclkctl);
552 debug("%s: VENDOR_CLOCK_CNTRL = 0x%08X\n", __func__, val);
553#endif /* T210 */
554#endif /* T30/T210 */
Stephen Warrenc76e9362016-09-13 10:45:44 -0600555}
556
Stephen Warren6d9ccbb2016-09-13 10:45:46 -0600557static void tegra_mmc_reset(struct tegra_mmc_priv *priv, struct mmc *mmc)
Tom Warren85f0ee42011-05-31 10:30:37 +0000558{
559 unsigned int timeout;
560 debug(" mmc_reset called\n");
561
562 /*
563 * RSTALL[0] : Software reset for all
564 * 1 = reset
565 * 0 = work
566 */
Stephen Warren6d9ccbb2016-09-13 10:45:46 -0600567 writeb(TEGRA_MMC_SWRST_SW_RESET_FOR_ALL, &priv->reg->swrst);
Tom Warren85f0ee42011-05-31 10:30:37 +0000568
Stephen Warren6d9ccbb2016-09-13 10:45:46 -0600569 priv->clock = 0;
Tom Warren85f0ee42011-05-31 10:30:37 +0000570
571 /* Wait max 100 ms */
572 timeout = 100;
573
574 /* hw clears the bit when it's done */
Stephen Warren6d9ccbb2016-09-13 10:45:46 -0600575 while (readb(&priv->reg->swrst) & TEGRA_MMC_SWRST_SW_RESET_FOR_ALL) {
Tom Warren85f0ee42011-05-31 10:30:37 +0000576 if (timeout == 0) {
577 printf("%s: timeout error\n", __func__);
578 return;
579 }
580 timeout--;
581 udelay(1000);
582 }
Tom Warren35ae07b2013-02-26 12:31:26 -0700583
584 /* Set SD bus voltage & enable bus power */
Stephen Warren6d9ccbb2016-09-13 10:45:46 -0600585 tegra_mmc_set_power(priv, fls(mmc->cfg->voltages) - 1);
Tom Warren35ae07b2013-02-26 12:31:26 -0700586 debug("%s: power control = %02X, host control = %02X\n", __func__,
Stephen Warren6d9ccbb2016-09-13 10:45:46 -0600587 readb(&priv->reg->pwrcon), readb(&priv->reg->hostctl));
Tom Warren35ae07b2013-02-26 12:31:26 -0700588
589 /* Make sure SDIO pads are set up */
Stephen Warren6d9ccbb2016-09-13 10:45:46 -0600590 tegra_mmc_pad_init(priv);
Tom Warren85f0ee42011-05-31 10:30:37 +0000591}
592
Simon Glass8c4c5c82017-04-23 20:02:11 -0600593static int tegra_mmc_init(struct udevice *dev)
Tom Warren85f0ee42011-05-31 10:30:37 +0000594{
Simon Glass8c4c5c82017-04-23 20:02:11 -0600595 struct tegra_mmc_priv *priv = dev_get_priv(dev);
596 struct mmc *mmc = mmc_get_mmc_dev(dev);
Tom Warren85f0ee42011-05-31 10:30:37 +0000597 unsigned int mask;
Tom Warrena66f7722016-09-13 10:45:48 -0600598 debug(" tegra_mmc_init called\n");
Tom Warren85f0ee42011-05-31 10:30:37 +0000599
Tom Warren2e86e812019-05-29 09:30:01 -0700600#if defined(CONFIG_TEGRA210)
601 priv->mmc_id = clock_decode_periph_id(dev);
602 if (priv->mmc_id == PERIPH_ID_NONE) {
603 printf("%s: Missing/invalid peripheral ID\n", __func__);
604 return -EINVAL;
605 }
606#endif
Stephen Warren6d9ccbb2016-09-13 10:45:46 -0600607 tegra_mmc_reset(priv, mmc);
Tom Warren85f0ee42011-05-31 10:30:37 +0000608
Marcel Ziswiler86708852017-03-25 01:18:22 +0100609#if defined(CONFIG_TEGRA124_MMC_DISABLE_EXT_LOOPBACK)
610 /*
611 * Disable the external clock loopback and use the internal one on
612 * SDMMC3 as per the SDMMC_VENDOR_MISC_CNTRL_0 register's SDMMC_SPARE1
613 * bits being set to 0xfffd according to the TRM.
614 *
615 * TODO(marcel.ziswiler@toradex.com): Move to device tree controlled
616 * approach once proper kernel integration made it mainline.
617 */
618 if (priv->reg == (void *)0x700b0400) {
619 mask = readl(&priv->reg->venmiscctl);
620 mask &= ~TEGRA_MMC_MISCON_ENABLE_EXT_LOOPBACK;
621 writel(mask, &priv->reg->venmiscctl);
622 }
623#endif
624
Stephen Warren6d9ccbb2016-09-13 10:45:46 -0600625 priv->version = readw(&priv->reg->hcver);
626 debug("host version = %x\n", priv->version);
Tom Warren85f0ee42011-05-31 10:30:37 +0000627
628 /* mask all */
Stephen Warren6d9ccbb2016-09-13 10:45:46 -0600629 writel(0xffffffff, &priv->reg->norintstsen);
630 writel(0xffffffff, &priv->reg->norintsigen);
Tom Warren85f0ee42011-05-31 10:30:37 +0000631
Stephen Warren6d9ccbb2016-09-13 10:45:46 -0600632 writeb(0xe, &priv->reg->timeoutcon); /* TMCLK * 2^27 */
Tom Warren85f0ee42011-05-31 10:30:37 +0000633 /*
634 * NORMAL Interrupt Status Enable Register init
635 * [5] ENSTABUFRDRDY : Buffer Read Ready Status Enable
636 * [4] ENSTABUFWTRDY : Buffer write Ready Status Enable
Anton staaf3ade2102011-11-10 11:56:50 +0000637 * [3] ENSTADMAINT : DMA boundary interrupt
Tom Warren85f0ee42011-05-31 10:30:37 +0000638 * [1] ENSTASTANSCMPLT : Transfre Complete Status Enable
639 * [0] ENSTACMDCMPLT : Command Complete Status Enable
640 */
Stephen Warren6d9ccbb2016-09-13 10:45:46 -0600641 mask = readl(&priv->reg->norintstsen);
Tom Warren85f0ee42011-05-31 10:30:37 +0000642 mask &= ~(0xffff);
Anton staaf0dfb31c2011-11-10 11:56:49 +0000643 mask |= (TEGRA_MMC_NORINTSTSEN_CMD_COMPLETE |
644 TEGRA_MMC_NORINTSTSEN_XFER_COMPLETE |
Anton staaf3ade2102011-11-10 11:56:50 +0000645 TEGRA_MMC_NORINTSTSEN_DMA_INTERRUPT |
Anton staaf0dfb31c2011-11-10 11:56:49 +0000646 TEGRA_MMC_NORINTSTSEN_BUFFER_WRITE_READY |
647 TEGRA_MMC_NORINTSTSEN_BUFFER_READ_READY);
Stephen Warren6d9ccbb2016-09-13 10:45:46 -0600648 writel(mask, &priv->reg->norintstsen);
Tom Warren85f0ee42011-05-31 10:30:37 +0000649
650 /*
651 * NORMAL Interrupt Signal Enable Register init
652 * [1] ENSTACMDCMPLT : Transfer Complete Signal Enable
653 */
Stephen Warren6d9ccbb2016-09-13 10:45:46 -0600654 mask = readl(&priv->reg->norintsigen);
Tom Warren85f0ee42011-05-31 10:30:37 +0000655 mask &= ~(0xffff);
Anton staaf0dfb31c2011-11-10 11:56:49 +0000656 mask |= TEGRA_MMC_NORINTSIGEN_XFER_COMPLETE;
Stephen Warren6d9ccbb2016-09-13 10:45:46 -0600657 writel(mask, &priv->reg->norintsigen);
Tom Warren85f0ee42011-05-31 10:30:37 +0000658
659 return 0;
660}
661
Simon Glass8c4c5c82017-04-23 20:02:11 -0600662static int tegra_mmc_getcd(struct udevice *dev)
Thierry Redingf1494112012-01-02 01:15:39 +0000663{
Simon Glass8c4c5c82017-04-23 20:02:11 -0600664 struct tegra_mmc_priv *priv = dev_get_priv(dev);
Thierry Redingf1494112012-01-02 01:15:39 +0000665
Tom Warren22562a42012-09-04 17:00:24 -0700666 debug("tegra_mmc_getcd called\n");
Thierry Redingf1494112012-01-02 01:15:39 +0000667
Stephen Warren6d9ccbb2016-09-13 10:45:46 -0600668 if (dm_gpio_is_valid(&priv->cd_gpio))
669 return dm_gpio_get_value(&priv->cd_gpio);
Thierry Redingf1494112012-01-02 01:15:39 +0000670
671 return 1;
672}
673
Simon Glass8c4c5c82017-04-23 20:02:11 -0600674static const struct dm_mmc_ops tegra_mmc_ops = {
Pantelis Antoniouc9e75912014-02-26 19:28:45 +0200675 .send_cmd = tegra_mmc_send_cmd,
676 .set_ios = tegra_mmc_set_ios,
Simon Glass8c4c5c82017-04-23 20:02:11 -0600677 .get_cd = tegra_mmc_getcd,
Pantelis Antoniouc9e75912014-02-26 19:28:45 +0200678};
679
Tom Warrena66f7722016-09-13 10:45:48 -0600680static int tegra_mmc_probe(struct udevice *dev)
Tom Warren85f0ee42011-05-31 10:30:37 +0000681{
Tom Warrena66f7722016-09-13 10:45:48 -0600682 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
Simon Glassfa20e932020-12-03 16:55:20 -0700683 struct tegra_mmc_plat *plat = dev_get_plat(dev);
Tom Warrena66f7722016-09-13 10:45:48 -0600684 struct tegra_mmc_priv *priv = dev_get_priv(dev);
Simon Glass8c4c5c82017-04-23 20:02:11 -0600685 struct mmc_config *cfg = &plat->cfg;
Stephen Warrenf79df4b2016-09-13 10:46:01 -0600686 int bus_width, ret;
Tom Warren85f0ee42011-05-31 10:30:37 +0000687
Simon Glass8c4c5c82017-04-23 20:02:11 -0600688 cfg->name = dev->name;
Tom Warren85f0ee42011-05-31 10:30:37 +0000689
Simon Glass9c3b0e42017-07-25 08:30:08 -0600690 bus_width = dev_read_u32_default(dev, "bus-width", 1);
Tom Warrena66f7722016-09-13 10:45:48 -0600691
Simon Glass8c4c5c82017-04-23 20:02:11 -0600692 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
693 cfg->host_caps = 0;
Tom Warrena66f7722016-09-13 10:45:48 -0600694 if (bus_width == 8)
Simon Glass8c4c5c82017-04-23 20:02:11 -0600695 cfg->host_caps |= MMC_MODE_8BIT;
Tom Warrena66f7722016-09-13 10:45:48 -0600696 if (bus_width >= 4)
Simon Glass8c4c5c82017-04-23 20:02:11 -0600697 cfg->host_caps |= MMC_MODE_4BIT;
698 cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
Tom Warren85f0ee42011-05-31 10:30:37 +0000699
700 /*
701 * min freq is for card identification, and is the highest
702 * low-speed SDIO card frequency (actually 400KHz)
703 * max freq is highest HS eMMC clock as per the SD/MMC spec
704 * (actually 52MHz)
Tom Warren85f0ee42011-05-31 10:30:37 +0000705 */
Simon Glass8c4c5c82017-04-23 20:02:11 -0600706 cfg->f_min = 375000;
707 cfg->f_max = 48000000;
Tom Warren85f0ee42011-05-31 10:30:37 +0000708
Simon Glass8c4c5c82017-04-23 20:02:11 -0600709 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
Pantelis Antoniou2c850462014-03-11 19:34:20 +0200710
Simon Glass9c3b0e42017-07-25 08:30:08 -0600711 priv->reg = (void *)dev_read_addr(dev);
Tom Warren9745cf82013-02-21 12:31:30 +0000712
Tom Warrena66f7722016-09-13 10:45:48 -0600713 ret = reset_get_by_name(dev, "sdhci", &priv->reset_ctl);
714 if (ret) {
715 debug("reset_get_by_name() failed: %d\n", ret);
716 return ret;
717 }
718 ret = clk_get_by_index(dev, 0, &priv->clk);
719 if (ret) {
720 debug("clk_get_by_index() failed: %d\n", ret);
721 return ret;
Stephen Warrend26e24d2016-08-05 16:10:33 -0600722 }
Tom Warrena66f7722016-09-13 10:45:48 -0600723
724 ret = reset_assert(&priv->reset_ctl);
725 if (ret)
726 return ret;
727 ret = clk_enable(&priv->clk);
728 if (ret)
729 return ret;
730 ret = clk_set_rate(&priv->clk, 20000000);
731 if (IS_ERR_VALUE(ret))
732 return ret;
733 ret = reset_deassert(&priv->reset_ctl);
734 if (ret)
735 return ret;
Tom Warren9745cf82013-02-21 12:31:30 +0000736
Tom Warrena66f7722016-09-13 10:45:48 -0600737 /* These GPIOs are optional */
Simon Glass9c3b0e42017-07-25 08:30:08 -0600738 gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio, GPIOD_IS_IN);
739 gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio, GPIOD_IS_IN);
740 gpio_request_by_name(dev, "power-gpios", 0, &priv->pwr_gpio,
741 GPIOD_IS_OUT);
Tom Warrena66f7722016-09-13 10:45:48 -0600742 if (dm_gpio_is_valid(&priv->pwr_gpio))
743 dm_gpio_set_value(&priv->pwr_gpio, 1);
Tom Warren9745cf82013-02-21 12:31:30 +0000744
Simon Glass8c4c5c82017-04-23 20:02:11 -0600745 upriv->mmc = &plat->mmc;
Tom Warren9745cf82013-02-21 12:31:30 +0000746
Simon Glass8c4c5c82017-04-23 20:02:11 -0600747 return tegra_mmc_init(dev);
748}
Tom Warren9745cf82013-02-21 12:31:30 +0000749
Simon Glass8c4c5c82017-04-23 20:02:11 -0600750static int tegra_mmc_bind(struct udevice *dev)
751{
Simon Glassfa20e932020-12-03 16:55:20 -0700752 struct tegra_mmc_plat *plat = dev_get_plat(dev);
Simon Glass8c4c5c82017-04-23 20:02:11 -0600753
754 return mmc_bind(dev, &plat->mmc, &plat->cfg);
Tom Warren9745cf82013-02-21 12:31:30 +0000755}
756
Tom Warrena66f7722016-09-13 10:45:48 -0600757static const struct udevice_id tegra_mmc_ids[] = {
758 { .compatible = "nvidia,tegra20-sdhci" },
759 { .compatible = "nvidia,tegra30-sdhci" },
760 { .compatible = "nvidia,tegra114-sdhci" },
761 { .compatible = "nvidia,tegra124-sdhci" },
762 { .compatible = "nvidia,tegra210-sdhci" },
763 { .compatible = "nvidia,tegra186-sdhci" },
764 { }
765};
Tom Warren9745cf82013-02-21 12:31:30 +0000766
Tom Warrena66f7722016-09-13 10:45:48 -0600767U_BOOT_DRIVER(tegra_mmc_drv) = {
768 .name = "tegra_mmc",
769 .id = UCLASS_MMC,
770 .of_match = tegra_mmc_ids,
Simon Glass8c4c5c82017-04-23 20:02:11 -0600771 .bind = tegra_mmc_bind,
Tom Warrena66f7722016-09-13 10:45:48 -0600772 .probe = tegra_mmc_probe,
Simon Glass8c4c5c82017-04-23 20:02:11 -0600773 .ops = &tegra_mmc_ops,
Simon Glass71fa5b42020-12-03 16:55:18 -0700774 .plat_auto = sizeof(struct tegra_mmc_plat),
Simon Glass8a2b47f2020-12-03 16:55:17 -0700775 .priv_auto = sizeof(struct tegra_mmc_priv),
Tom Warrena66f7722016-09-13 10:45:48 -0600776};