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git01.mediatek.com / filogic / uboot / 2cd2ff0384b630955aaee5415a6076e3f615a46b / . / arch / arm / dts / r8a779h0.dtsi
blob: a896bc27f5afb00b35ccc77f8457b6af3b752e76 [file] [log] [blame]
Hai Pham3a81a0b2024-01-28 16:52:06 +0100[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2/*
3 * Device Tree Source for the R-Car V4M (R8A779H0) SoC
4 *
5 * Copyright (C) 2023 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/clock/renesas,r8a779h0-cpg-mssr.h>
9#include <dt-bindings/interrupt-controller/arm-gic.h>
10#include <dt-bindings/power/renesas,r8a779h0-sysc.h>
11
12/ {
13 compatible = "renesas,r8a779h0";
14 #address-cells = <2>;
15 #size-cells = <2>;
16
17 cpus {
18 #address-cells = <1>;
19 #size-cells = <0>;
20
21 a76_0: cpu@0 {
22 compatible = "arm,cortex-a76";
23 reg = <0>;
24 device_type = "cpu";
25 power-domains = <&sysc R8A779H0_PD_A1E0D0C0>;
26 };
27 };
28
29 extal_clk: extal-clk {
30 compatible = "fixed-clock";
31 #clock-cells = <0>;
32 /* This value must be overridden by the board */
33 clock-frequency = <0>;
34 };
35
36 extalr_clk: extalr-clk {
37 compatible = "fixed-clock";
38 #clock-cells = <0>;
39 /* This value must be overridden by the board */
40 clock-frequency = <0>;
41 };
42
43 pmu-a76 {
44 compatible = "arm,cortex-a76-pmu";
45 interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
46 };
47
48 /* External SCIF clock - to be overridden by boards that provide it */
49 scif_clk: scif-clk {
50 compatible = "fixed-clock";
51 #clock-cells = <0>;
52 clock-frequency = <0>;
53 };
54
55 soc: soc {
56 compatible = "simple-bus";
57 interrupt-parent = <&gic>;
58 #address-cells = <2>;
59 #size-cells = <2>;
60 ranges;
61
62 pfc: pinctrl@e6050000 {
63 compatible = "renesas,pfc-r8a779h0";
64 reg = <0 0xe6050000 0 0x16c>, <0 0xe6050800 0 0x16c>,
65 <0 0xe6058000 0 0x16c>, <0 0xe6058800 0 0x16c>,
66 <0 0xe6060000 0 0x16c>, <0 0xe6060800 0 0x16c>,
67 <0 0xe6061000 0 0x16c>, <0 0xe6061800 0 0x16c>;
68 };
69
70 gpio0: gpio@e6050180 {
71 compatible = "renesas,gpio-r8a779h0",
72 "renesas,rcar-gen4-gpio";
73 reg = <0 0xe6050180 0 0x54>;
74 interrupts = <GIC_SPI 619 IRQ_TYPE_LEVEL_HIGH>;
75 #gpio-cells = <2>;
76 gpio-controller;
77 gpio-ranges = <&pfc 0 0 19>;
78 #interrupt-cells = <2>;
79 interrupt-controller;
80 clocks = <&cpg CPG_MOD 915>;
81 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
82 resets = <&cpg 915>;
83 };
84
85 gpio1: gpio@e6050980 {
86 compatible = "renesas,gpio-r8a779h0",
87 "renesas,rcar-gen4-gpio";
88 reg = <0 0xe6050980 0 0x54>;
89 interrupts = <GIC_SPI 623 IRQ_TYPE_LEVEL_HIGH>;
90 #gpio-cells = <2>;
91 gpio-controller;
92 gpio-ranges = <&pfc 0 32 30>;
93 #interrupt-cells = <2>;
94 interrupt-controller;
95 clocks = <&cpg CPG_MOD 915>;
96 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
97 resets = <&cpg 915>;
98 };
99
100 gpio2: gpio@e6058180 {
101 compatible = "renesas,gpio-r8a779h0",
102 "renesas,rcar-gen4-gpio";
103 reg = <0 0xe6058180 0 0x54>;
104 interrupts = <GIC_SPI 627 IRQ_TYPE_LEVEL_HIGH>;
105 #gpio-cells = <2>;
106 gpio-controller;
107 gpio-ranges = <&pfc 0 64 20>;
108 #interrupt-cells = <2>;
109 interrupt-controller;
110 clocks = <&cpg CPG_MOD 916>;
111 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
112 resets = <&cpg 916>;
113 };
114
115 gpio3: gpio@e6058980 {
116 compatible = "renesas,gpio-r8a779h0",
117 "renesas,rcar-gen4-gpio";
118 reg = <0 0xe6058980 0 0x54>;
119 interrupts = <GIC_SPI 631 IRQ_TYPE_LEVEL_HIGH>;
120 #gpio-cells = <2>;
121 gpio-controller;
122 gpio-ranges = <&pfc 0 96 32>;
123 #interrupt-cells = <2>;
124 interrupt-controller;
125 clocks = <&cpg CPG_MOD 916>;
126 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
127 resets = <&cpg 916>;
128 };
129
130 gpio4: gpio@e6060180 {
131 compatible = "renesas,gpio-r8a779h0",
132 "renesas,rcar-gen4-gpio";
133 reg = <0 0xe6060180 0 0x54>;
134 interrupts = <GIC_SPI 635 IRQ_TYPE_LEVEL_HIGH>;
135 #gpio-cells = <2>;
136 gpio-controller;
137 gpio-ranges = <&pfc 0 128 25>;
138 #interrupt-cells = <2>;
139 interrupt-controller;
140 clocks = <&cpg CPG_MOD 917>;
141 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
142 resets = <&cpg 917>;
143 };
144
145 gpio5: gpio@e6060980 {
146 compatible = "renesas,gpio-r8a779h0",
147 "renesas,rcar-gen4-gpio";
148 reg = <0 0xe6060980 0 0x54>;
149 interrupts = <GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH>;
150 #gpio-cells = <2>;
151 gpio-controller;
152 gpio-ranges = <&pfc 0 160 21>;
153 #interrupt-cells = <2>;
154 interrupt-controller;
155 clocks = <&cpg CPG_MOD 917>;
156 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
157 resets = <&cpg 917>;
158 };
159
160 gpio6: gpio@e6061180 {
161 compatible = "renesas,gpio-r8a779h0",
162 "renesas,rcar-gen4-gpio";
163 reg = <0 0xe6061180 0 0x54>;
164 interrupts = <GIC_SPI 643 IRQ_TYPE_LEVEL_HIGH>;
165 #gpio-cells = <2>;
166 gpio-controller;
167 gpio-ranges = <&pfc 0 192 21>;
168 #interrupt-cells = <2>;
169 interrupt-controller;
170 clocks = <&cpg CPG_MOD 917>;
171 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
172 resets = <&cpg 917>;
173 };
174
175 gpio7: gpio@e6061980 {
176 compatible = "renesas,gpio-r8a779h0",
177 "renesas,rcar-gen4-gpio";
178 reg = <0 0xe6061980 0 0x54>;
179 interrupts = <GIC_SPI 647 IRQ_TYPE_LEVEL_HIGH>;
180 #gpio-cells = <2>;
181 gpio-controller;
182 gpio-ranges = <&pfc 0 224 21>;
183 #interrupt-cells = <2>;
184 interrupt-controller;
185 clocks = <&cpg CPG_MOD 917>;
186 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
187 resets = <&cpg 917>;
188 };
189
190 cpg: clock-controller@e6150000 {
191 compatible = "renesas,r8a779h0-cpg-mssr";
192 reg = <0 0xe6150000 0 0x4000>;
193 clocks = <&extal_clk>, <&extalr_clk>;
194 clock-names = "extal", "extalr";
195 #clock-cells = <2>;
196 #power-domain-cells = <0>;
197 #reset-cells = <1>;
198 };
199
200 rst: reset-controller@e6160000 {
201 compatible = "renesas,r8a779h0-rst";
202 reg = <0 0xe6160000 0 0x4000>;
203 };
204
205 sysc: system-controller@e6180000 {
206 compatible = "renesas,r8a779h0-sysc";
207 reg = <0 0xe6180000 0 0x4000>;
208 #power-domain-cells = <1>;
209 };
210
211 i2c0: i2c@e6500000 {
212 compatible = "renesas,i2c-r8a779h0",
213 "renesas,rcar-gen4-i2c";
214 reg = <0 0xe6500000 0 0x40>;
215 interrupts = <GIC_SPI 610 IRQ_TYPE_LEVEL_HIGH>;
216 clocks = <&cpg CPG_MOD 518>;
217 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
218 resets = <&cpg 518>;
219 i2c-scl-internal-delay-ns = <110>;
220 #address-cells = <1>;
221 #size-cells = <0>;
222 status = "disabled";
223 };
224
225 i2c1: i2c@e6508000 {
226 compatible = "renesas,i2c-r8a779h0",
227 "renesas,rcar-gen4-i2c";
228 reg = <0 0xe6508000 0 0x40>;
229 interrupts = <GIC_SPI 611 IRQ_TYPE_LEVEL_HIGH>;
230 clocks = <&cpg CPG_MOD 519>;
231 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
232 resets = <&cpg 519>;
233 i2c-scl-internal-delay-ns = <110>;
234 #address-cells = <1>;
235 #size-cells = <0>;
236 status = "disabled";
237 };
238
239 i2c2: i2c@e6510000 {
240 compatible = "renesas,i2c-r8a779h0",
241 "renesas,rcar-gen4-i2c";
242 reg = <0 0xe6510000 0 0x40>;
243 interrupts = <GIC_SPI 612 IRQ_TYPE_LEVEL_HIGH>;
244 clocks = <&cpg CPG_MOD 520>;
245 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
246 resets = <&cpg 520>;
247 i2c-scl-internal-delay-ns = <110>;
248 #address-cells = <1>;
249 #size-cells = <0>;
250 status = "disabled";
251 };
252
253 i2c3: i2c@e66d0000 {
254 compatible = "renesas,i2c-r8a779h0",
255 "renesas,rcar-gen4-i2c";
256 reg = <0 0xe66d0000 0 0x40>;
257 interrupts = <GIC_SPI 613 IRQ_TYPE_LEVEL_HIGH>;
258 clocks = <&cpg CPG_MOD 521>;
259 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
260 resets = <&cpg 521>;
261 i2c-scl-internal-delay-ns = <110>;
262 #address-cells = <1>;
263 #size-cells = <0>;
264 status = "disabled";
265 };
266
267 hscif0: serial@e6540000 {
268 compatible = "renesas,hscif-r8a779h0",
269 "renesas,rcar-gen4-hscif", "renesas,hscif";
270 reg = <0 0xe6540000 0 0x60>;
271 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
272 clocks = <&cpg CPG_MOD 514>,
273 <&cpg CPG_CORE R8A779H0_CLK_SASYNCPERD1>,
274 <&scif_clk>;
275 clock-names = "fck", "brg_int", "scif_clk";
276 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
277 resets = <&cpg 514>;
278 status = "disabled";
279 };
280
281 avb0: ethernet@e6800000 {
282 compatible = "renesas,etheravb-r8a779h0",
283 "renesas,etheravb-rcar-gen4";
284 reg = <0 0xe6800000 0 0x800>;
285 interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
286 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
287 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
288 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
289 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
290 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
291 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
292 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
293 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
294 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
295 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
296 <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>,
297 <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
298 <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>,
299 <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>,
300 <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
301 <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>,
302 <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>,
303 <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>,
304 <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>,
305 <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>,
306 <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>,
307 <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>,
308 <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>,
309 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
310 interrupt-names = "ch0", "ch1", "ch2", "ch3",
311 "ch4", "ch5", "ch6", "ch7",
312 "ch8", "ch9", "ch10", "ch11",
313 "ch12", "ch13", "ch14", "ch15",
314 "ch16", "ch17", "ch18", "ch19",
315 "ch20", "ch21", "ch22", "ch23",
316 "ch24";
317 clocks = <&cpg CPG_MOD 211>;
318 power-domains = <&sysc R8A779H0_PD_C4>;
319 resets = <&cpg 211>;
320 phy-mode = "rgmii";
321 rx-internal-delay-ps = <0>;
322 tx-internal-delay-ps = <0>;
323 #address-cells = <1>;
324 #size-cells = <0>;
325 status = "disabled";
326 };
327
328 avb1: ethernet@e6810000 {
329 compatible = "renesas,etheravb-r8a779h0",
330 "renesas,etheravb-rcar-gen4";
331 reg = <0 0xe6810000 0 0x800>;
332 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>,
333 <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>,
334 <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>,
335 <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>,
336 <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>,
337 <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>,
338 <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>,
339 <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>,
340 <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>,
341 <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>,
342 <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>,
343 <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>,
344 <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>,
345 <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>,
346 <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
347 <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>,
348 <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>,
349 <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>,
350 <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>,
351 <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>,
352 <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>,
353 <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>,
354 <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>,
355 <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>,
356 <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>;
357 interrupt-names = "ch0", "ch1", "ch2", "ch3",
358 "ch4", "ch5", "ch6", "ch7",
359 "ch8", "ch9", "ch10", "ch11",
360 "ch12", "ch13", "ch14", "ch15",
361 "ch16", "ch17", "ch18", "ch19",
362 "ch20", "ch21", "ch22", "ch23",
363 "ch24";
364 clocks = <&cpg CPG_MOD 212>;
365 power-domains = <&sysc R8A779H0_PD_C4>;
366 resets = <&cpg 212>;
367 phy-mode = "rgmii";
368 rx-internal-delay-ps = <0>;
369 tx-internal-delay-ps = <0>;
370 #address-cells = <1>;
371 #size-cells = <0>;
372 status = "disabled";
373 };
374
375 avb2: ethernet@e6820000 {
376 compatible = "renesas,etheravb-r8a779h0",
377 "renesas,etheravb-rcar-gen4";
378 reg = <0 0xe6820000 0 0x1000>;
379 interrupts = <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>,
380 <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>,
381 <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>,
382 <GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>,
383 <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>,
384 <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>,
385 <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>,
386 <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>,
387 <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>,
388 <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>,
389 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
390 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
391 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
392 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
393 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
394 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
395 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
396 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
397 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
398 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
399 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
400 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
401 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
402 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
403 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>;
404 interrupt-names = "ch0", "ch1", "ch2", "ch3",
405 "ch4", "ch5", "ch6", "ch7",
406 "ch8", "ch9", "ch10", "ch11",
407 "ch12", "ch13", "ch14", "ch15",
408 "ch16", "ch17", "ch18", "ch19",
409 "ch20", "ch21", "ch22", "ch23",
410 "ch24";
411 clocks = <&cpg CPG_MOD 213>;
412 power-domains = <&sysc R8A779H0_PD_C4>;
413 resets = <&cpg 213>;
414 phy-mode = "rgmii";
415 rx-internal-delay-ps = <0>;
416 tx-internal-delay-ps = <0>;
417 #address-cells = <1>;
418 #size-cells = <0>;
419 status = "disabled";
420 };
421
422 mmc0: mmc@ee140000 {
423 compatible = "renesas,sdhi-r8a779h0",
424 "renesas,rcar-gen4-sdhi";
425 reg = <0 0xee140000 0 0x2000>;
426 interrupts = <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>;
427 clocks = <&cpg CPG_MOD 706>,
428 <&cpg CPG_CORE R8A779H0_CLK_SD0H>;
429 clock-names = "core", "clkh";
430 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
431 resets = <&cpg 706>;
432 max-frequency = <200000000>;
433 status = "disabled";
434 };
435
436 gic: interrupt-controller@f1000000 {
437 compatible = "arm,gic-v3";
438 #interrupt-cells = <3>;
439 #address-cells = <0>;
440 interrupt-controller;
441 reg = <0x0 0xf1000000 0 0x20000>,
442 <0x0 0xf1060000 0 0x110000>;
443 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
444 };
445
446 prr: chipid@fff00044 {
447 compatible = "renesas,prr";
448 reg = <0 0xfff00044 0 4>;
449 };
450 };
451
452 timer {
453 compatible = "arm,armv8-timer";
454 interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
455 <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
456 <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
457 <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>,
458 <&gic GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>;
459 };
460};