Gitiles
Code Review Sign In
git01.mediatek.com / filogic / uboot / 2cd2ff0384b630955aaee5415a6076e3f615a46b / . / arch / arm / dts / imx8mm-verdin-wifi-dev-u-boot.dtsi
blob: 38db56059d69187cbc299999df3375ef2dd94326 [file] [log] [blame]
Marcel Ziswiler2712c782022-07-21 15:41:23 +0200[diff] [blame]1// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2/*
3 * Copyright 2020-2022 Toradex
4 */
5
6#include "imx8mm-u-boot.dtsi"
7
8/ {
Emanuele Ghidoliff939c22024-02-23 10:11:40 +0100[diff] [blame]9 aliases {
10 eeprom0 = &eeprom_module;
11 eeprom1 = &eeprom_carrier_board;
12 eeprom2 = &eeprom_display_adapter;
13 };
14
Emanuele Ghidoli26b5cba2024-02-23 10:11:41 +0100[diff] [blame]15 sysinfo {
16 compatible = "toradex,sysinfo";
17 };
18
Marcel Ziswiler2712c782022-07-21 15:41:23 +0200[diff] [blame]19 wdt-reboot {
20 compatible = "wdt-reboot";
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]21 bootph-pre-ram;
Marcel Ziswiler2712c782022-07-21 15:41:23 +0200[diff] [blame]22 wdt = <&wdog1>;
23 };
24};
25
Marcel Ziswiler2712c782022-07-21 15:41:23 +0200[diff] [blame]26&{/soc@0/bus@30800000/i2c@30a20000/pmic@25} {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]27 bootph-pre-ram;
Marcel Ziswiler2712c782022-07-21 15:41:23 +0200[diff] [blame]28};
29
30&{/soc@0/bus@30800000/i2c@30a20000/pmic@25/regulators} {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]31 bootph-pre-ram;
Marcel Ziswiler2712c782022-07-21 15:41:23 +0200[diff] [blame]32};
33
Marcel Ziswiler8d322832023-08-23 00:17:25 +0200[diff] [blame]34&aips4 {
35 bootph-pre-ram;
36};
37
Marcel Ziswiler2712c782022-07-21 15:41:23 +0200[diff] [blame]38&binman_uboot {
39 offset = <0x5fc00>;
40};
41
42&gpio1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]43 bootph-pre-ram;
Marcel Ziswiler2712c782022-07-21 15:41:23 +0200[diff] [blame]44};
45
46&gpio2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]47 bootph-pre-ram;
Marcel Ziswiler2712c782022-07-21 15:41:23 +0200[diff] [blame]48};
49
50&gpio3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]51 bootph-pre-ram;
Marcel Ziswiler2712c782022-07-21 15:41:23 +0200[diff] [blame]52};
53
54&gpio4 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]55 bootph-pre-ram;
Marcel Ziswiler2712c782022-07-21 15:41:23 +0200[diff] [blame]56};
57
58&gpio5 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]59 bootph-pre-ram;
Andrejs Cainikovs5ab25a12023-07-11 11:09:16 +0200[diff] [blame]60
61 ctrl-sleep-moci-hog {
62 bootph-pre-ram;
63 };
Marcel Ziswiler2712c782022-07-21 15:41:23 +0200[diff] [blame]64};
65
66&i2c1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]67 bootph-pre-ram;
Marcel Ziswiler2712c782022-07-21 15:41:23 +0200[diff] [blame]68
69 eeprom_module: eeprom@50 {
70 compatible = "i2c-eeprom";
71 pagesize = <16>;
72 reg = <0x50>;
73 };
74};
75
76&i2c2 {
77 status = "okay";
78};
79
80&i2c4 {
81 /* EEPROM on display adapter (MIPI DSI Display Adapter) */
82 eeprom_display_adapter: eeprom@50 {
83 compatible = "i2c-eeprom";
84 pagesize = <16>;
85 reg = <0x50>;
86 };
87
88 /* EEPROM on carrier board */
89 eeprom_carrier_board: eeprom@57 {
90 compatible = "i2c-eeprom";
91 pagesize = <16>;
92 reg = <0x57>;
93 };
94};
95
Andrejs Cainikovs5ab25a12023-07-11 11:09:16 +0200[diff] [blame]96&pinctrl_ctrl_sleep_moci {
97 bootph-pre-ram;
98};
99
Marcel Ziswiler2712c782022-07-21 15:41:23 +0200[diff] [blame]100&pinctrl_i2c1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]101 bootph-pre-ram;
Marcel Ziswiler2712c782022-07-21 15:41:23 +0200[diff] [blame]102};
103
104&pinctrl_pmic {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]105 bootph-pre-ram;
Marcel Ziswiler2712c782022-07-21 15:41:23 +0200[diff] [blame]106};
107
108&pinctrl_uart1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]109 bootph-pre-ram;
Marcel Ziswiler2712c782022-07-21 15:41:23 +0200[diff] [blame]110};
111
112&pinctrl_usdhc1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]113 bootph-pre-ram;
Marcel Ziswiler2712c782022-07-21 15:41:23 +0200[diff] [blame]114};
115
116&pinctrl_usdhc2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]117 bootph-pre-ram;
Marcel Ziswiler2712c782022-07-21 15:41:23 +0200[diff] [blame]118};
119
120&pinctrl_wdog {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]121 bootph-pre-ram;
Marcel Ziswiler2712c782022-07-21 15:41:23 +0200[diff] [blame]122};
123
124&uart1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]125 bootph-pre-ram;
Marcel Ziswiler2712c782022-07-21 15:41:23 +0200[diff] [blame]126};
127
Marcel Ziswiler8d322832023-08-23 00:17:25 +0200[diff] [blame]128&usbmisc1 {
129 bootph-pre-ram;
130};
131
132/* Verdin USB_1 */
133&usbotg1 {
134 bootph-pre-ram;
135};
136
137&usbphynop1 {
138 bootph-pre-ram;
139};
140
Marcel Ziswiler2712c782022-07-21 15:41:23 +0200[diff] [blame]141&usdhc1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]142 bootph-pre-ram;
Marcel Ziswiler2712c782022-07-21 15:41:23 +0200[diff] [blame]143};
144
145&usdhc2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]146 bootph-pre-ram;
Marcel Ziswiler2712c782022-07-21 15:41:23 +0200[diff] [blame]147};
148
149&usdhc3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]150 bootph-pre-ram;
Marcel Ziswiler2712c782022-07-21 15:41:23 +0200[diff] [blame]151};
152
153&wdog1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]154 bootph-pre-ram;
Marcel Ziswiler2712c782022-07-21 15:41:23 +0200[diff] [blame]155};