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git01.mediatek.com / filogic / uboot / 2cd2ff0384b630955aaee5415a6076e3f615a46b / . / arch / arm / dts / imx8mm-data-modul-edm-sbc-u-boot.dtsi
blob: a235e088fa4baf1deff50d7f70d7dca00508d203 [file] [log] [blame]
Marek Vasut0b16ba52022-04-12 17:26:01 +0200[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright 2022 Marek Vasut <marex@denx.de>
4 */
5
6#include "imx8mm-u-boot.dtsi"
7
8/ {
9 aliases {
10 eeprom0 = &eeprom;
11 mmc0 = &usdhc3; /* eMMC */
12 mmc1 = &usdhc2; /* MicroSD */
13 };
14
15 config {
16 dmo,ram-coding-gpios = <&gpio2 8 0>, <&gpio2 1 0>, <&gpio2 0 0>;
17 };
18
19 wdt-reboot {
20 compatible = "wdt-reboot";
21 wdt = <&wdog1>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]22 bootph-pre-ram;
Marek Vasut0b16ba52022-04-12 17:26:01 +0200[diff] [blame]23 };
24};
25
26&buck4_reg {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]27 bootph-pre-ram;
Marek Vasut0b16ba52022-04-12 17:26:01 +0200[diff] [blame]28};
29
30&buck5_reg {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]31 bootph-pre-ram;
Marek Vasut0b16ba52022-04-12 17:26:01 +0200[diff] [blame]32};
33
34&i2c1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]35 bootph-pre-ram;
Marek Vasut0b16ba52022-04-12 17:26:01 +0200[diff] [blame]36};
37
38&pinctrl_hog_sbc {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]39 bootph-pre-ram;
Marek Vasut0b16ba52022-04-12 17:26:01 +0200[diff] [blame]40};
41
42&pinctrl_i2c1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]43 bootph-pre-ram;
Marek Vasut0b16ba52022-04-12 17:26:01 +0200[diff] [blame]44};
45
46&pinctrl_i2c1_gpio {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]47 bootph-pre-ram;
Marek Vasut0b16ba52022-04-12 17:26:01 +0200[diff] [blame]48};
49
50&pinctrl_pmic {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]51 bootph-pre-ram;
Marek Vasut0b16ba52022-04-12 17:26:01 +0200[diff] [blame]52};
53
54&pinctrl_uart3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]55 bootph-pre-ram;
Marek Vasut0b16ba52022-04-12 17:26:01 +0200[diff] [blame]56};
57
58&pinctrl_usdhc2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]59 bootph-pre-ram;
Marek Vasut0b16ba52022-04-12 17:26:01 +0200[diff] [blame]60};
61
62&pinctrl_usdhc3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]63 bootph-pre-ram;
Marek Vasut0b16ba52022-04-12 17:26:01 +0200[diff] [blame]64};
65
66&pmic {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]67 bootph-pre-ram;
Marek Vasut0b16ba52022-04-12 17:26:01 +0200[diff] [blame]68
69 regulators {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]70 bootph-pre-ram;
Marek Vasut0b16ba52022-04-12 17:26:01 +0200[diff] [blame]71 };
72};
73
74&gpio1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]75 bootph-pre-ram;
Marek Vasut0b16ba52022-04-12 17:26:01 +0200[diff] [blame]76};
77
78&gpio2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]79 bootph-pre-ram;
Marek Vasut602accd2023-12-18 19:02:14 +0100[diff] [blame]80
81 dsi-reset-hog {
82 bootph-pre-ram;
83 gpio-hog;
84 output-high;
85 gpios = <2 GPIO_ACTIVE_LOW>;
86 line-name = "DSI_RESET_1V8#";
87 };
88
89
90 dsi-irq-hog {
91 bootph-pre-ram;
92 gpio-hog;
93 input;
94 gpios = <3 GPIO_ACTIVE_LOW>;
95 line-name = "DSI_IRQ_1V8#";
96 };
97
98 graphics-prsnt-hog {
99 bootph-pre-ram;
100 gpio-hog;
101 input;
102 gpios = <7 GPIO_ACTIVE_LOW>;
103 line-name = "GRAPHICS_PRSNT_1V8#";
104 };
Marek Vasut0b16ba52022-04-12 17:26:01 +0200[diff] [blame]105};
106
107&gpio3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]108 bootph-pre-ram;
Marek Vasut602accd2023-12-18 19:02:14 +0100[diff] [blame]109
110 bl-enable-hog {
111 bootph-pre-ram;
112 gpio-hog;
113 output-low;
114 gpios = <0 GPIO_ACTIVE_HIGH>;
115 line-name = "BL_ENABLE_1V8";
116 };
117
118 tft-enable-hog {
119 bootph-pre-ram;
120 gpio-hog;
121 output-low;
122 gpios = <6 GPIO_ACTIVE_HIGH>;
123 line-name = "TFT_ENABLE_1V8";
124 };
125
126 graphics-gpio0-hog {
127 bootph-pre-ram;
128 gpio-hog;
129 input;
130 gpios = <7 GPIO_ACTIVE_HIGH>;
131 line-name = "GRAPHICS_GPIO0_1V8";
132 };
Marek Vasut0b16ba52022-04-12 17:26:01 +0200[diff] [blame]133};
134
135&gpio4 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]136 bootph-pre-ram;
Marek Vasut0b16ba52022-04-12 17:26:01 +0200[diff] [blame]137};
138
139&gpio5 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]140 bootph-pre-ram;
Marek Vasut0b16ba52022-04-12 17:26:01 +0200[diff] [blame]141};
142
143&uart3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]144 bootph-pre-ram;
Marek Vasut0b16ba52022-04-12 17:26:01 +0200[diff] [blame]145};
146
147&usbotg1 {
148 dr_mode = "peripheral";
149};
150
151&usdhc2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]152 bootph-pre-ram;
Marek Vasut0b16ba52022-04-12 17:26:01 +0200[diff] [blame]153 sd-uhs-sdr104;
154 sd-uhs-ddr50;
155};
156
157&usdhc3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]158 bootph-pre-ram;
Marek Vasut0b16ba52022-04-12 17:26:01 +0200[diff] [blame]159 mmc-hs400-1_8v;
160 mmc-hs400-enhanced-strobe;
161};
162
163&wdog1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]164 bootph-pre-ram;
Marek Vasut0b16ba52022-04-12 17:26:01 +0200[diff] [blame]165};