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git01.mediatek.com / filogic / uboot / 2cbc87340514505014510c13e053f040ef3598bf / . / board / netta / dsp.c
blob: 2bea3adeae360df225b8024e8930199d19469865 [file] [log] [blame]
wdenk3902d702004-04-15 18:22:41 +0000[diff] [blame]1/*
2 * Intracom TI6711 DSP
3 */
4
5#include <common.h>
6#include <post.h>
7
8#include "mpc8xx.h"
9
10struct ram_range {
11 u32 start;
12 u32 size;
13};
14
15static const struct ram_range int_ram[] = {
16 { 0x00000000U, 0x00010000U },
17};
18
19static const struct ram_range ext_ram[] = {
20 { 0x80000000U, 0x00100000U },
21};
22
23static const struct ram_range ranges[] = {
24 { 0x00000000U, 0x00010000U },
25 { 0x80000000U, 0x00100000U },
26};
27
28/*******************************************************************************************************/
29
30static inline int addr_in_int_ram(u32 addr)
31{
32 int i;
33
34 for (i = 0; i < sizeof(int_ram)/sizeof(int_ram[0]); i++)
35 if (addr >= int_ram[i].start && addr < int_ram[i].start + int_ram[i].size)
36 return 1;
37
38 return 0;
39}
40
41static inline int addr_in_ext_ram(u32 addr)
42{
43 int i;
44
45 for (i = 0; i < sizeof(ext_ram)/sizeof(ext_ram[0]); i++)
46 if (addr >= ext_ram[i].start && addr < ext_ram[i].start + ext_ram[i].size)
47 return 1;
48
49 return 0;
50}
51
52/*******************************************************************************************************/
53
54#define DSP_HPIC 0x0
55#define DSP_HPIA 0x4
56#define DSP_HPID1 0x8
57#define DSP_HPID2 0xC
58
59static u32 dummy_delay;
60static volatile u32 *ti6711_delay = &dummy_delay;
61
62static inline void dsp_go_slow(void)
63{
64 volatile memctl8xx_t *memctl = &((immap_t *)CFG_IMMR)->im_memctl;
65
66 memctl->memc_or2 |= OR_SCY_15_CLK | OR_TRLX;
67 memctl->memc_or5 |= OR_SCY_15_CLK | OR_TRLX;
68
69 ti6711_delay = (u32 *)DUMMY_BASE;
70}
71
72static inline void dsp_go_fast(void)
73{
74 volatile memctl8xx_t *memctl = &((immap_t *)CFG_IMMR)->im_memctl;
75
76 memctl->memc_or2 = (memctl->memc_or2 & ~(OR_SCY_15_CLK | OR_TRLX)) | OR_SCY_3_CLK;
77 memctl->memc_or5 = (memctl->memc_or5 & ~(OR_SCY_15_CLK | OR_TRLX)) | OR_SCY_0_CLK;
78
79 ti6711_delay = &dummy_delay;
80}
81
82/*******************************************************************************************************/
83
84static inline void dsp_delay(void)
85{
86 /* perform ti6711_delay chip select read to have a small delay */
87 (void) *(volatile u32 *)ti6711_delay;
88}
89
90static inline u16 dsp_read_hpic(void)
91{
92 return *((volatile u16 *)DSP_BASE);
93}
94
95static inline void dsp_write_hpic(u16 val)
96{
97 *((volatile u16 *)DSP_BASE) = val;
98}
99
100static inline void dsp_reset(void)
101{
102 ((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat &= ~(1 << (15 - 7));
103 udelay(250);
104 ((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat |= (1 << (15 - 7));
105 udelay(250);
106}
107
108static inline void dsp_init_hpic(void)
109{
110 int i;
111 volatile u16 *p;
112
113 dsp_go_slow();
114
115 i = 0;
116 while (i < 1000 && (dsp_read_hpic() & 0x08) == 0) {
117 dsp_delay();
118 i++;
119 }
120 dsp_delay();
121
122 /* write control register */
123 p = (volatile u16 *)DSP_BASE;
124 p[0] = 0x0000;
125 dsp_delay();
126 p[1] = 0x0000;
127 dsp_delay();
128
129 dsp_go_fast();
130}
131
132static inline void dsp_wait_hrdy(void)
133{
134 int i;
135
136 i = 0;
137 while (i < 1000 && (dsp_read_hpic() & 0x08) == 0) {
138 dsp_delay();
139 i++;
140 }
141}
142
143static inline u32 dsp_read_hpic_word(u32 addr)
144{
145 u32 val;
146 volatile u16 *p;
147
148 p = (volatile u16 *)((volatile u8 *)DSP_BASE + addr);
149
150 val = ((u32) p[0] << 16);
151 dsp_delay();
152
153 val |= p[1];
154 dsp_delay();
155
156 return val;
157}
158
159static inline u16 dsp_read_hpic_hi_hword(u32 addr)
160{
161 return *(volatile u16 *)((volatile u8 *)DSP_BASE + addr);
162}
163
164static inline u16 dsp_read_hpic_lo_hword(u32 addr)
165{
166 return *(volatile u16 *)((volatile u8 *)DSP_BASE + addr + 2);
167}
168
169static inline void dsp_write_hpic_word(u32 addr, u32 val)
170{
171 volatile u16 *p;
172
173 p = (volatile u16 *)((volatile u8 *)DSP_BASE + addr);
174 p[0] = (u16)(val >> 16);
175 dsp_delay();
176
177 p[1] = (u16)val;
178 dsp_delay();
179}
180
181static inline void dsp_write_hpic_hi_hword(u32 addr, u16 val_h)
182{
183 *(volatile u16 *)((volatile u8 *)DSP_BASE + addr) = val_h;
184}
185
186static inline void dsp_write_hpic_lo_hword(u32 addr, u16 val_l)
187{
188 *(volatile u16 *)((volatile u8 *)DSP_BASE + addr + 2) = val_l;
189}
190
191/********************************************************************/
192
193static inline void c62_write_word(u32 addr, u32 val)
194{
195 dsp_write_hpic_hi_hword(DSP_HPIA, (u16)(addr >> 16));
196 dsp_delay();
197 dsp_write_hpic_lo_hword(DSP_HPIA, (u16)addr);
198 dsp_delay();
199
200 dsp_wait_hrdy();
201 dsp_delay();
202
203 dsp_write_hpic_hi_hword(DSP_HPID2, (u16)(val >> 16));
204 dsp_delay();
205
206 dsp_wait_hrdy();
207 dsp_delay();
208
209 dsp_write_hpic_lo_hword(DSP_HPID2, (u16)val);
210 dsp_delay();
211}
212
213static u32 c62_read_word(u32 addr)
214{
215 u32 val;
216
217 dsp_write_hpic_hi_hword(DSP_HPIA, (u16)(addr >> 16));
218 dsp_delay();
219 dsp_write_hpic_lo_hword(DSP_HPIA, (u16)addr);
220 dsp_delay();
221
222 /* FETCH */
223 dsp_write_hpic(0x10);
224 dsp_delay();
225
226 dsp_wait_hrdy();
227 dsp_delay();
228
229 val = (u32)dsp_read_hpic_hi_hword(DSP_HPID2) << 16;
230 dsp_delay();
231
232 dsp_wait_hrdy();
233 dsp_delay();
234
235 val |= dsp_read_hpic_lo_hword(DSP_HPID2);
236 dsp_delay();
237
238 return val;
239}
240
241static inline void c62_read(u32 addr, u32 *buffer, int numdata)
242{
243 int i;
244
245 if (numdata <= 0)
246 return;
247
248 for (i = 0; i < numdata; i++) {
249 *buffer++ = c62_read_word(addr);
250 addr += 4;
251 }
252}
253
254static inline u32 c62_checksum(u32 addr, int numdata)
255{
256 int i;
257 u32 chksum;
258
259 chksum = 0;
260 for (i = 0; i < numdata; i++) {
261 chksum += c62_read_word(addr);
262 addr += 4;
263 }
264
265 return chksum;
266}
267
268static inline void c62_write(u32 addr, const u32 *buffer, int numdata)
269{
270 int i;
271
272 if (numdata <= 0)
273 return;
274
275 for (i = 0; i < numdata; i++) {
276 c62_write_word(addr, *buffer++);
277 addr += 4;
278 }
279}
280
281static inline int c62_write_word_validated(u32 addr, u32 val)
282{
283 c62_write_word(addr, val);
284 return c62_read_word(addr) == val ? 0 : -1;
285}
286
287static inline int c62_write_validated(u32 addr, const u32 *buffer, int numdata)
288{
289 int i, r;
290
291 if (numdata <= 0)
292 return 0;
293
294 for (i = 0; i < numdata; i++) {
295 r = c62_write_word_validated(addr, *buffer++);
296 if (r < 0)
297 return r;
298 addr += 4;
299 }
300 return 0;
301}
302
303/***********************************************************************************************************/
304
305static const u8 bootstrap_rbin[5084] = {
306 0x52, 0x42, 0x49, 0x4e, 0xc5, 0xa9, 0x9f, 0x1a, 0x00, 0x00, 0x00, 0x02,
307 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x20, 0x00,
308 0x00, 0x00, 0x11, 0xc0, 0x00, 0x17, 0x94, 0x2a, 0x00, 0x00, 0x00, 0x6a,
309 0x00, 0x00, 0x03, 0x62, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
310 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00,
311 0x00, 0x18, 0x00, 0xe2, 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00,
312 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
313 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0xe2,
314 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
315 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
316 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0xe2, 0x00, 0x00, 0x60, 0x00,
317 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
318 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
319 0x00, 0x18, 0x00, 0xe2, 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00,
320 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
321 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0xe2,
322 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
323 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
324 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0xe2, 0x00, 0x00, 0x60, 0x00,
325 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
326 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
327 0x00, 0x18, 0x00, 0xe2, 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00,
328 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
329 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0xe2,
330 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
331 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
332 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0xe2, 0x00, 0x00, 0x60, 0x00,
333 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
334 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
335 0x00, 0x18, 0x00, 0xe2, 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00,
336 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
337 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0xe2,
338 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
339 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
340 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0xe2, 0x00, 0x00, 0x60, 0x00,
341 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
342 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
343 0x00, 0x18, 0x00, 0xe2, 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00,
344 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
345 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0xe2,
346 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
347 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
348 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0xe2, 0x00, 0x00, 0x60, 0x00,
349 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
350 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
351 0x00, 0x17, 0x94, 0x2a, 0x00, 0x00, 0x00, 0x6a, 0x00, 0x00, 0x03, 0x62,
352 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
353 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x18, 0x00, 0xe2,
354 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
355 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
356 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0xe2, 0x00, 0x00, 0x60, 0x00,
357 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
358 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
359 0x00, 0x18, 0x00, 0xe2, 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00,
360 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
361 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0xe2,
362 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
363 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
364 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0xe2, 0x00, 0x00, 0x60, 0x00,
365 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
366 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
367 0x00, 0x18, 0x00, 0xe2, 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00,
368 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
369 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0xe2,
370 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
371 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
372 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0xe2, 0x00, 0x00, 0x60, 0x00,
373 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
374 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
375 0x00, 0x18, 0x00, 0xe2, 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00,
376 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
377 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0xe2,
378 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
379 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
380 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0xe2, 0x00, 0x00, 0x60, 0x00,
381 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
382 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
383 0x00, 0x18, 0x00, 0xe2, 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00,
384 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
385 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0xe2,
386 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
387 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
388 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0xe2, 0x00, 0x00, 0x60, 0x00,
389 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
390 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
391 0x00, 0x18, 0x00, 0xe2, 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00,
392 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
393 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x90, 0x10, 0x5a,
394 0x00, 0x19, 0x2e, 0x28, 0x00, 0x00, 0x00, 0x68, 0x00, 0x00, 0x02, 0x64,
395 0x02, 0x00, 0x00, 0xaa, 0x02, 0x10, 0xac, 0xe2, 0x00, 0x00, 0x20, 0x00,
396 0x00, 0x00, 0x02, 0x64, 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x9f, 0x7a,
397 0x30, 0x00, 0x08, 0x10, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x04, 0x28,
398 0x00, 0x00, 0xc6, 0x69, 0x02, 0x16, 0x4c, 0xa2, 0x02, 0x00, 0x90, 0x7a,
399 0x00, 0x10, 0x02, 0xe4, 0x00, 0x00, 0x60, 0x00, 0x00, 0x02, 0xd6, 0xc8,
400 0x00, 0x10, 0x02, 0xf4, 0x03, 0x10, 0x02, 0xe6, 0x00, 0x00, 0x60, 0x00,
401 0x03, 0x1a, 0xf7, 0xca, 0x03, 0x10, 0x02, 0xf6, 0x00, 0x00, 0x04, 0x28,
402 0x00, 0x00, 0xc6, 0x69, 0x02, 0x16, 0x4c, 0xa2, 0x02, 0x00, 0x90, 0x7a,
403 0x02, 0x90, 0x02, 0xe6, 0x00, 0x00, 0x60, 0x00, 0x02, 0x97, 0xcf, 0x5a,
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712 0x93, 0x1c, 0x36, 0x74, 0x00, 0x00, 0x00, 0x00, 0x03, 0x20, 0x02, 0x65,
713 0x02, 0x19, 0x2a, 0x29, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x60, 0x79,
714 0x01, 0xa0, 0x36, 0x65, 0x02, 0x00, 0x00, 0x68, 0x80, 0x87, 0xe0, 0x59,
715 0x90, 0x14, 0x02, 0x75, 0x02, 0x90, 0x01, 0xa0, 0x00, 0x14, 0x02, 0x64,
716 0x00, 0x00, 0x40, 0x00, 0x03, 0x1c, 0x36, 0x74, 0x00, 0x00, 0x60, 0x78,
717 0x00, 0x14, 0x02, 0x74, 0x00, 0x19, 0x2a, 0x28, 0x00, 0x00, 0x00, 0x68,
718 0x00, 0x18, 0xe0, 0x29, 0x00, 0x00, 0x02, 0x66, 0x00, 0x00, 0x00, 0x68,
719 0x00, 0x00, 0x40, 0x00, 0x31, 0x80, 0x80, 0x59, 0x32, 0x19, 0x2e, 0x2a,
720 0x32, 0x00, 0x00, 0x6a, 0x31, 0x90, 0x02, 0xf4, 0x30, 0x02, 0x9d, 0x41,
721 0x32, 0x19, 0x30, 0x2a, 0x32, 0x00, 0x00, 0x6a, 0x30, 0x10, 0x02, 0xf4,
722 0x30, 0x00, 0x09, 0x12, 0x00, 0x00, 0x80, 0x00, 0x02, 0x80, 0x00, 0xfa,
723 0x02, 0x80, 0xc0, 0x6a, 0x03, 0x14, 0x02, 0xe6, 0x02, 0x00, 0x08, 0x2a,
724 0x00, 0x00, 0x40, 0x00, 0x02, 0x18, 0x8d, 0xfa, 0x02, 0x14, 0x02, 0xf6,
725 0x00, 0x00, 0x00, 0xf8, 0x00, 0x00, 0xc0, 0x68, 0x01, 0x80, 0x02, 0x64,
726 0x00, 0x00, 0x60, 0x00, 0x01, 0x8d, 0x0d, 0xd8, 0x01, 0x80, 0x02, 0x74,
727 0x0f, 0xff, 0xf9, 0x90, 0x00, 0x00, 0x80, 0x00, 0x00, 0x0c, 0x03, 0x62,
728 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
729 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
730};
731
732static int load_bootstrap(void)
733{
734 const u8 *s = bootstrap_rbin;
735 u32 l = sizeof(bootstrap_rbin);
736 const u8 *data, *hdr, *h;
737 u32 chksum, chksum2;
738 int i, j, rangenr;
739 u32 start, length;
740
741 if (l < 12) {
742 printf("bootstrap image corrupted. (too short header)\n");
743 return -1;
744 }
745
746 chksum = ((u32)s[4] << 24) | ((u32)s[5] << 16) | ((u32)s[ 6] << 8) | (u32)s[ 7];
747 rangenr = ((u32)s[8] << 24) | ((u32)s[9] << 16) | ((u32)s[10] << 8) | (u32)s[11];
748 s += 12; l -= 12;
749
750 hdr = s;
751 s += 8 * rangenr; l -= 8 * rangenr;
752 data = s;
753
754 /* validate bootstrap image */
755 h = hdr; s = data; chksum2 = 0;
756 for (i = 0; i < rangenr; i++) {
757 start = ((u32)h[0] << 24) | ((u32)h[1] << 16) | ((u32)h[2] << 8) | (u32)h[3];
758 length = ((u32)h[4] << 24) | ((u32)h[5] << 16) | ((u32)h[6] << 8) | (u32)h[7];
759 h += 8;
760
761 /* too short */
762 if (l < length) {
763 printf("bootstrap image corrupted. (too short data)\n");
764 return -1;
765 }
766 l -= length;
767
768 j = (int)length / 4;
769 while (j-- > 0) {
770 chksum2 += ((u32)s[0] << 24) | ((u32)s[1] << 16) | ((u32)s[2] << 8) | (u32)s[3];
771 s += 4;
772 }
773 }
774
775 /* checksum must match */
776 if (chksum != chksum2) {
777 printf("bootstrap image corrupted. (checksum error)\n");
778 return -1;
779 }
780
781 /* nothing must be left */
782 if (l != 0) {
783 printf("bootstrap image corrupted. (garbage at the end)\n");
784 return -1;
785 }
786
787 /* write the image */
788 h = hdr;
789 s = data;
790 for (i = 0; i < rangenr; i++) {
791 start = ((u32)h[0] << 24) | ((u32)h[1] << 16) | ((u32)h[2] << 8) | (u32)h[3];
792 length = ((u32)h[4] << 24) | ((u32)h[5] << 16) | ((u32)h[6] << 8) | (u32)h[7];
793 h += 8;
794 c62_write(start, (u32 *)s, length / 4);
795 s += length;
796 }
797
798 /* and now validate checksum */
799 h = hdr;
800 s = data;
801 chksum2 = 0;
802 for (i = 0; i < rangenr; i++) {
803 start = ((u32)h[0] << 24) | ((u32)h[1] << 16) | ((u32)h[2] << 8) | (u32)h[3];
804 length = ((u32)h[4] << 24) | ((u32)h[5] << 16) | ((u32)h[6] << 8) | (u32)h[7];
805 h += 8;
806 chksum2 += c62_checksum(start, length / 4);
807 s += length;
808 }
809
810 /* checksum must match */
811 if (chksum != chksum2) {
812 printf("bootstrap in DSP memory is corrupted\n");
813 return -1;
814 }
815
816 return 0;
817}
818
819struct host_init {
820 u32 master_mode;
821 struct {
822 u8 port_id;
823 u8 slot_id;
824 } ch_serial_map[32];
825 u32 clk_divider[2];
826 /* pll */
827 u32 initmode;
828 u32 pllm;
829 u32 div[4];
830 u32 oscdiv1;
831 u32 unused[10];
832};
833
834const struct host_init hi_default = {
835 .master_mode =
836#if !defined(CONFIG_NETTA_ISDN)
837 -1,
838#else
839 0,
840#endif
841
842 .ch_serial_map = {
843 [ 0] = { .port_id = 2, .slot_id = 16 },
844 [ 1] = { .port_id = 2, .slot_id = 17 },
845 [ 2] = { .port_id = 2, .slot_id = 18 },
846 [ 3] = { .port_id = 2, .slot_id = 19 },
847 [ 4] = { .port_id = 2, .slot_id = 20 },
848 [ 5] = { .port_id = 2, .slot_id = 21 },
849 [ 6] = { .port_id = 2, .slot_id = 22 },
850 [ 7] = { .port_id = 2, .slot_id = 23 },
851 [ 8] = { .port_id = 2, .slot_id = 24 },
852 [ 9] = { .port_id = 2, .slot_id = 25 },
853 [10] = { .port_id = 2, .slot_id = 26 },
854 [11] = { .port_id = 2, .slot_id = 27 },
855 [12] = { .port_id = 2, .slot_id = 28 },
856 [13] = { .port_id = 2, .slot_id = 29 },
857 [14] = { .port_id = 2, .slot_id = 30 },
858 [15] = { .port_id = 2, .slot_id = 31 },
859 },
860
861 /*
862 dsp_clk(xin, pllm) = xin * pllm
863 serial_clk(xin, pllm, div) = (dsp_clk(xin, pllm) / 2) / (div + 1)
864 */
865
866 .clk_divider = {
867 [0] = 47, /* must be 2048Hz */
868 [1] = 47,
869 },
870
871 .initmode = 1,
872 .pllm =
873#if !defined(CONFIG_NETTA_ISDN)
874 8, /* for =~ 25MHz 8 */
875#else
876 4,
877#endif
878 .div = {
879 [0] = 0x8000,
880 [1] = 0x8000, /* for =~ 25MHz 0x8000 */
881 [2] = 0x8001, /* for =~ 25MHz 0x8001 */
882 [3] = 0x8001, /* for =~ 25MHz 0x8001 */
883 },
884
885 .oscdiv1 = 0,
886};
887
888static void hi_write(const struct host_init *hi)
889{
890 u32 hi_buf[1 + sizeof(*hi) / sizeof(u32)];
891 u32 *s;
892 u32 chksum;
893 int i;
894
895 memset(hi_buf, 0, sizeof(hi_buf));
896
897 s = hi_buf;
898 s++;
899 *s++ = hi->master_mode;
900 for (i = 0; i < (sizeof(hi->ch_serial_map) / sizeof(hi->ch_serial_map[0])) / 2; i++)
901 *s++ = ((u32)hi->ch_serial_map[i * 2 + 1].slot_id << 24) | ((u32)hi->ch_serial_map[i * 2 + 1].port_id << 16) |
902 ((u32)hi->ch_serial_map[i * 2 + 0].slot_id << 8) | (u32)hi->ch_serial_map[i * 2 + 0].port_id;
903
904 for (i = 0; i < sizeof(hi->clk_divider)/sizeof(hi->clk_divider[0]); i++)
905 *s++ = hi->clk_divider[i];
906
907 *s++ = hi->initmode;
908 *s++ = hi->pllm;
909 for (i = 0; i < sizeof(hi->div)/sizeof(hi->div[0]); i++)
910 *s++ = hi->div[i];
911 *s++ = hi->oscdiv1;
912
913 chksum = 0;
914 for (i = 1; i < sizeof(hi_buf)/sizeof(hi_buf[0]); i++)
915 chksum += hi_buf[i];
916 hi_buf[0] = -chksum;
917
918 c62_write(0x1000, hi_buf, sizeof(hi_buf) / sizeof(hi_buf[0]));
919}
920
921static void run_bootstrap(void)
922{
923 dsp_go_slow();
924
925 hi_write(&hi_default);
926
927 /* signal interrupt */
928 dsp_write_hpic(0x0002);
929 dsp_delay();
930
931 dsp_go_fast();
932}
933
934/***********************************************************************************************************/
935
936int board_post_dsp(int flags)
937{
938 u32 ramS, ramE;
939 u32 data, data2;
940 int i, j, k, r;
941
942 dsp_reset();
943 dsp_init_hpic();
944 dsp_go_slow();
945
946 data = 0x11223344;
947 dsp_write_hpic_word(DSP_HPIA, data);
948 data2 = dsp_read_hpic_word(DSP_HPIA);
949 if (data2 != 0x11223344) {
950 printf("HPIA: ** ERROR; wrote 0x%08X read 0x%08X **\n", data, data2);
951 goto err;
952 }
953
954 data = 0xFFEEDDCC;
955 dsp_write_hpic_word(DSP_HPIA, data);
956 data2 = dsp_read_hpic_word(DSP_HPIA);
957 if (data2 != 0xFFEEDDCC) {
958 printf("HPIA: ** ERROR; wrote 0x%08X read 0x%08X **\n", data, data2);
959 goto err;
960 }
961
962 r = load_bootstrap();
963 if (r < 0) {
964 printf("BOOTSTRAP: ** ERROR ** failed to load\n");
965 goto err;
966 }
967
968 run_bootstrap();
969
970 dsp_go_fast();
971
972 printf(" ");
973
974 /* test RAMs */
975 for (k = 0; k < sizeof(ranges)/sizeof(ranges[0]); k++) {
976
977 ramS = ranges[k].start;
978 ramE = ranges[k].start + ranges[k].size;
979
980 for (j = 0; j < 3; j++) {
981
982 printf("\b\b\b\bR%d.%d", k, j);
983
984 for (i = ramS; i < ramE; i += 4) {
985
986 data = 0;
987 switch (j) {
988 case 0: data = 0xAA55AA55; break;
989 case 1: data = 0x55AA55AA; break;
990 case 2: data = (u32)i; break;
991 }
992
993 c62_write_word(i, data);
994 data2 = c62_read_word(i);
995 if (data != data2) {
996 printf(" ** ERROR at 0x%08X; wrote 0x%08X read 0x%08X **\n", i, data, data2);
997 goto err;
998 }
999 }
1000 }
1001 }
1002
1003 printf("\b\b\b\b \b\b\b\bOK\n");
1004
1005 /* XXX assume that this works */
1006 load_bootstrap();
1007 run_bootstrap();
1008 dsp_go_fast();
1009
1010 return 0;
1011
1012err:
1013 return -1;
1014}
1015
1016int board_dsp_reset(void)
1017{
1018 int r;
1019
1020 dsp_reset();
1021 dsp_init_hpic();
1022 dsp_go_slow();
1023 r = load_bootstrap();
1024 if (r < 0)
1025 return r;
1026
1027 run_bootstrap();
1028 dsp_go_fast();
1029
1030 return 0;
1031}