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git01.mediatek.com / filogic / uboot / 2c9b05ddcca3debd07fbe1a8c4e7937acf79fdfd / . / post / cache_8xx.S
blob: 2d41b5566a8f9f7f2b0bb567c0a601908da6bb50 [file] [log] [blame]
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]1/*
2 * Copyright (C) 2002 Wolfgang Denk <wd@denx.de>
3 *
4 * See file CREDITS for list of people who contributed to this
5 * project.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 */
22
23#include <config.h>
24
25#ifdef CONFIG_POST
26#if defined(CONFIG_MPC823) || \
27 defined(CONFIG_MPC850) || \
28 defined(CONFIG_MPC855) || \
29 defined(CONFIG_MPC860) || \
wdenk2c9b05d2003-09-10 22:30:53 +0000[diff] [blame^]30 defined(CONFIG_MPC862)
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]31
32#include <post.h>
33#include <ppc_asm.tmpl>
34#include <ppc_defs.h>
35#include <asm/cache.h>
36
37#if CONFIG_POST & CFG_POST_CACHE
38
39 .text
40
41cache_post_dinvalidate:
42 lis r10, IDC_INVALL@h
43 mtspr DC_CST, r10
44 blr
45
46cache_post_iinvalidate:
47 lis r10, IDC_INVALL@h
48 mtspr IC_CST, r10
49 isync
50 blr
51
52cache_post_ddisable:
53 lis r10, IDC_DISABLE@h
54 mtspr DC_CST, r10
55 blr
56
57cache_post_dwb:
58 lis r10, IDC_ENABLE@h
59 mtspr DC_CST, r10
60 lis r10, DC_CFWT@h
61 mtspr DC_CST, r10
62 blr
63
64cache_post_dwt:
65 lis r10, IDC_ENABLE@h
66 mtspr DC_CST, r10
67 lis r10, DC_SFWT@h
68 mtspr DC_CST, r10
69 blr
70
71cache_post_idisable:
72 lis r10, IDC_DISABLE@h
73 mtspr IC_CST, r10
74 isync
75 blr
76
77cache_post_ienable:
78 lis r10, IDC_ENABLE@h
79 mtspr IC_CST, r10
80 isync
81 blr
82
83cache_post_iunlock:
84 lis r10, IDC_UNALL@h
85 mtspr IC_CST, r10
86 isync
87 blr
88
89cache_post_ilock:
90 mtspr IC_ADR, r3
91 lis r10, IDC_LDLCK@h
92 mtspr IC_CST, r10
93 isync
94 blr
95
96/*
97 * turn on the data cache
98 * switch the data cache to write-back or write-through mode
99 * invalidate the data cache
100 * write the negative pattern to a cached area
101 * read the area
102 *
103 * The negative pattern must be read at the last step
104 */
105 .global cache_post_test1
106cache_post_test1:
107 mflr r0
108 stw r0, 4(r1)
109
110 stwu r3, -4(r1)
111 stwu r4, -4(r1)
112
113 bl cache_post_dwb
114 bl cache_post_dinvalidate
115
116 /* Write the negative pattern to the test area */
117 lwz r0, 0(r1)
118 mtctr r0
119 li r0, 0xff
120 lwz r3, 4(r1)
121 subi r3, r3, 1
1221:
123 stbu r0, 1(r3)
124 bdnz 1b
125
126 /* Read the test area */
127 lwz r0, 0(r1)
128 mtctr r0
129 lwz r4, 4(r1)
130 subi r4, r4, 1
131 li r3, 0
1321:
133 lbzu r0, 1(r4)
134 cmpli cr0, r0, 0xff
135 beq 2f
136 li r3, -1
137 b 3f
1382:
139 bdnz 1b
1403:
141
142 bl cache_post_ddisable
143 bl cache_post_dinvalidate
144
145 addi r1, r1, 8
146
147 lwz r0, 4(r1)
148 mtlr r0
149 blr
150
151/*
152 * turn on the data cache
153 * switch the data cache to write-back or write-through mode
154 * invalidate the data cache
155 * write the zero pattern to a cached area
156 * turn off the data cache
157 * write the negative pattern to the area
158 * turn on the data cache
159 * read the area
160 *
161 * The negative pattern must be read at the last step
162 */
163 .global cache_post_test2
164cache_post_test2:
165 mflr r0
166 stw r0, 4(r1)
167
168 stwu r3, -4(r1)
169 stwu r4, -4(r1)
170
171 bl cache_post_dwb
172 bl cache_post_dinvalidate
173
174 /* Write the zero pattern to the test area */
175 lwz r0, 0(r1)
176 mtctr r0
177 li r0, 0
178 lwz r3, 4(r1)
179 subi r3, r3, 1
1801:
181 stbu r0, 1(r3)
182 bdnz 1b
183
184 bl cache_post_ddisable
185
186 /* Write the negative pattern to the test area */
187 lwz r0, 0(r1)
188 mtctr r0
189 li r0, 0xff
190 lwz r3, 4(r1)
191 subi r3, r3, 1
1921:
193 stbu r0, 1(r3)
194 bdnz 1b
195
196 bl cache_post_dwb
197
198 /* Read the test area */
199 lwz r0, 0(r1)
200 mtctr r0
201 lwz r4, 4(r1)
202 subi r4, r4, 1
203 li r3, 0
2041:
205 lbzu r0, 1(r4)
206 cmpli cr0, r0, 0xff
207 beq 2f
208 li r3, -1
209 b 3f
2102:
211 bdnz 1b
2123:
213
214 bl cache_post_ddisable
215 bl cache_post_dinvalidate
216
217 addi r1, r1, 8
218
219 lwz r0, 4(r1)
220 mtlr r0
221 blr
222
223/*
224 * turn on the data cache
225 * switch the data cache to write-through mode
226 * invalidate the data cache
227 * write the zero pattern to a cached area
228 * flush the data cache
229 * write the negative pattern to the area
230 * turn off the data cache
231 * read the area
232 *
233 * The negative pattern must be read at the last step
234 */
235 .global cache_post_test3
236cache_post_test3:
237 mflr r0
238 stw r0, 4(r1)
239
240 stwu r3, -4(r1)
241 stwu r4, -4(r1)
242
243 bl cache_post_ddisable
244 bl cache_post_dinvalidate
245
246 /* Write the zero pattern to the test area */
247 lwz r0, 0(r1)
248 mtctr r0
249 li r0, 0
250 lwz r3, 4(r1)
251 subi r3, r3, 1
2521:
253 stbu r0, 1(r3)
254 bdnz 1b
255
256 bl cache_post_dwt
257 bl cache_post_dinvalidate
258
259 /* Write the negative pattern to the test area */
260 lwz r0, 0(r1)
261 mtctr r0
262 li r0, 0xff
263 lwz r3, 4(r1)
264 subi r3, r3, 1
2651:
266 stbu r0, 1(r3)
267 bdnz 1b
268
269 bl cache_post_ddisable
270 bl cache_post_dinvalidate
271
272 /* Read the test area */
273 lwz r0, 0(r1)
274 mtctr r0
275 lwz r4, 4(r1)
276 subi r4, r4, 1
277 li r3, 0
2781:
279 lbzu r0, 1(r4)
280 cmpli cr0, r0, 0xff
281 beq 2f
282 li r3, -1
283 b 3f
2842:
285 bdnz 1b
2863:
287
288 addi r1, r1, 8
289
290 lwz r0, 4(r1)
291 mtlr r0
292 blr
293
294/*
295 * turn on the data cache
296 * switch the data cache to write-back mode
297 * invalidate the data cache
298 * write the negative pattern to a cached area
299 * flush the data cache
300 * write the zero pattern to the area
301 * invalidate the data cache
302 * read the area
303 *
304 * The negative pattern must be read at the last step
305 */
306 .global cache_post_test4
307cache_post_test4:
308 mflr r0
309 stw r0, 4(r1)
310
311 stwu r3, -4(r1)
312 stwu r4, -4(r1)
313
314 bl cache_post_ddisable
315 bl cache_post_dinvalidate
316
317 /* Write the negative pattern to the test area */
318 lwz r0, 0(r1)
319 mtctr r0
320 li r0, 0xff
321 lwz r3, 4(r1)
322 subi r3, r3, 1
3231:
324 stbu r0, 1(r3)
325 bdnz 1b
326
327 bl cache_post_dwb
328 bl cache_post_dinvalidate
329
330 /* Write the zero pattern to the test area */
331 lwz r0, 0(r1)
332 mtctr r0
333 li r0, 0
334 lwz r3, 4(r1)
335 subi r3, r3, 1
3361:
337 stbu r0, 1(r3)
338 bdnz 1b
339
340 bl cache_post_ddisable
341 bl cache_post_dinvalidate
342
343 /* Read the test area */
344 lwz r0, 0(r1)
345 mtctr r0
346 lwz r4, 4(r1)
347 subi r4, r4, 1
348 li r3, 0
3491:
350 lbzu r0, 1(r4)
351 cmpli cr0, r0, 0xff
352 beq 2f
353 li r3, -1
354 b 3f
3552:
356 bdnz 1b
3573:
358
359 addi r1, r1, 8
360
361 lwz r0, 4(r1)
362 mtlr r0
363 blr
364
365cache_post_test5_1:
366 li r3, 0
367cache_post_test5_2:
368 li r3, -1
369
370/*
371 * turn on the instruction cache
372 * unlock the entire instruction cache
373 * invalidate the instruction cache
374 * lock a branch instruction in the instruction cache
375 * replace the branch instruction with "nop"
376 * jump to the branch instruction
377 * check that the branch instruction was executed
378*/
379 .global cache_post_test5
380cache_post_test5:
381 mflr r0
382 stw r0, 4(r1)
383
384 bl cache_post_ienable
385 bl cache_post_iunlock
386 bl cache_post_iinvalidate
387
388 /* Compute r9 = cache_post_test5_reloc */
389 bl cache_post_test5_reloc
390cache_post_test5_reloc:
391 mflr r9
392
393 /* Copy the test instruction to cache_post_test5_data */
394 lis r3, (cache_post_test5_1 - cache_post_test5_reloc)@h
395 ori r3, r3, (cache_post_test5_1 - cache_post_test5_reloc)@l
396 add r3, r3, r9
397 lis r4, (cache_post_test5_data - cache_post_test5_reloc)@h
398 ori r4, r4, (cache_post_test5_data - cache_post_test5_reloc)@l
399 add r4, r4, r9
400 lwz r0, 0(r3)
401 stw r0, 0(r4)
402
403 bl cache_post_iinvalidate
404
405 /* Lock the branch instruction */
406 lis r3, (cache_post_test5_data - cache_post_test5_reloc)@h
407 ori r3, r3, (cache_post_test5_data - cache_post_test5_reloc)@l
408 add r3, r3, r9
409 bl cache_post_ilock
410
411 /* Replace the test instruction */
412 lis r3, (cache_post_test5_2 - cache_post_test5_reloc)@h
413 ori r3, r3, (cache_post_test5_2 - cache_post_test5_reloc)@l
414 add r3, r3, r9
415 lis r4, (cache_post_test5_data - cache_post_test5_reloc)@h
416 ori r4, r4, (cache_post_test5_data - cache_post_test5_reloc)@l
417 add r4, r4, r9
418 lwz r0, 0(r3)
419 stw r0, 0(r4)
420
421 bl cache_post_iinvalidate
422
423 /* Execute to the test instruction */
424cache_post_test5_data:
425 nop
426
427 bl cache_post_iunlock
428
429 lwz r0, 4(r1)
430 mtlr r0
431 blr
432
433cache_post_test6_1:
434 li r3, -1
435cache_post_test6_2:
436 li r3, 0
437
438/*
439 * turn on the instruction cache
440 * unlock the entire instruction cache
441 * invalidate the instruction cache
442 * lock a branch instruction in the instruction cache
443 * replace the branch instruction with "nop"
444 * jump to the branch instruction
445 * check that the branch instruction was executed
446 */
447 .global cache_post_test6
448cache_post_test6:
449 mflr r0
450 stw r0, 4(r1)
451
452 bl cache_post_ienable
453 bl cache_post_iunlock
454 bl cache_post_iinvalidate
455
456 /* Compute r9 = cache_post_test6_reloc */
457 bl cache_post_test6_reloc
458cache_post_test6_reloc:
459 mflr r9
460
461 /* Copy the test instruction to cache_post_test6_data */
462 lis r3, (cache_post_test6_1 - cache_post_test6_reloc)@h
463 ori r3, r3, (cache_post_test6_1 - cache_post_test6_reloc)@l
464 add r3, r3, r9
465 lis r4, (cache_post_test6_data - cache_post_test6_reloc)@h
466 ori r4, r4, (cache_post_test6_data - cache_post_test6_reloc)@l
467 add r4, r4, r9
468 lwz r0, 0(r3)
469 stw r0, 0(r4)
470
471 bl cache_post_iinvalidate
472
473 /* Replace the test instruction */
474 lis r3, (cache_post_test6_2 - cache_post_test6_reloc)@h
475 ori r3, r3, (cache_post_test6_2 - cache_post_test6_reloc)@l
476 add r3, r3, r9
477 lis r4, (cache_post_test6_data - cache_post_test6_reloc)@h
478 ori r4, r4, (cache_post_test6_data - cache_post_test6_reloc)@l
479 add r4, r4, r9
480 lwz r0, 0(r3)
481 stw r0, 0(r4)
482
483 bl cache_post_iinvalidate
484
485 /* Execute to the test instruction */
486cache_post_test6_data:
487 nop
488
489 lwz r0, 4(r1)
490 mtlr r0
491 blr
492
wdenk2c9b05d2003-09-10 22:30:53 +0000[diff] [blame^]493#endif /* CONFIG_MPC823 || MPC850 || MPC855 || MPC860 */
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]494#endif /* CONFIG_POST & CFG_POST_CACHE */
495#endif /* CONFIG_POST */