Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Simon Glass | fc0ba2d | 2015-01-01 16:18:15 -0700 | [diff] [blame] | 2 | /* |
| 3 | * (C) Copyright 2014 Google, Inc |
Simon Glass | fc0ba2d | 2015-01-01 16:18:15 -0700 | [diff] [blame] | 4 | */ |
| 5 | |
| 6 | #include <common.h> |
Simon Glass | ed38aef | 2020-05-10 11:40:03 -0600 | [diff] [blame] | 7 | #include <command.h> |
Simon Glass | 7403c26 | 2020-07-17 08:48:22 -0600 | [diff] [blame] | 8 | #include <log.h> |
Simon Glass | fc0ba2d | 2015-01-01 16:18:15 -0700 | [diff] [blame] | 9 | #include <asm/msr.h> |
Simon Glass | 7403c26 | 2020-07-17 08:48:22 -0600 | [diff] [blame] | 10 | #include <asm/mp.h> |
Simon Glass | fc0ba2d | 2015-01-01 16:18:15 -0700 | [diff] [blame] | 11 | #include <asm/mtrr.h> |
| 12 | |
| 13 | static const char *const mtrr_type_name[MTRR_TYPE_COUNT] = { |
| 14 | "Uncacheable", |
| 15 | "Combine", |
| 16 | "2", |
| 17 | "3", |
| 18 | "Through", |
| 19 | "Protect", |
| 20 | "Back", |
| 21 | }; |
| 22 | |
Simon Glass | 7403c26 | 2020-07-17 08:48:22 -0600 | [diff] [blame] | 23 | static void read_mtrrs(void *arg) |
Simon Glass | fc0ba2d | 2015-01-01 16:18:15 -0700 | [diff] [blame] | 24 | { |
Simon Glass | 7403c26 | 2020-07-17 08:48:22 -0600 | [diff] [blame] | 25 | struct mtrr_info *info = arg; |
| 26 | |
| 27 | mtrr_read_all(info); |
| 28 | } |
| 29 | |
| 30 | static int do_mtrr_list(int cpu_select) |
| 31 | { |
| 32 | struct mtrr_info info; |
| 33 | int ret; |
Simon Glass | fc0ba2d | 2015-01-01 16:18:15 -0700 | [diff] [blame] | 34 | int i; |
| 35 | |
| 36 | printf("Reg Valid Write-type %-16s %-16s %-16s\n", "Base ||", |
| 37 | "Mask ||", "Size ||"); |
Simon Glass | 7403c26 | 2020-07-17 08:48:22 -0600 | [diff] [blame] | 38 | memset(&info, '\0', sizeof(info)); |
| 39 | ret = mp_run_on_cpus(cpu_select, read_mtrrs, &info); |
| 40 | if (ret) |
| 41 | return log_msg_ret("run", ret); |
Simon Glass | fc0ba2d | 2015-01-01 16:18:15 -0700 | [diff] [blame] | 42 | for (i = 0; i < MTRR_COUNT; i++) { |
| 43 | const char *type = "Invalid"; |
| 44 | uint64_t base, mask, size; |
| 45 | bool valid; |
| 46 | |
Simon Glass | 7403c26 | 2020-07-17 08:48:22 -0600 | [diff] [blame] | 47 | base = info.mtrr[i].base; |
| 48 | mask = info.mtrr[i].mask; |
Simon Glass | fc0ba2d | 2015-01-01 16:18:15 -0700 | [diff] [blame] | 49 | size = ~mask & ((1ULL << CONFIG_CPU_ADDR_BITS) - 1); |
| 50 | size |= (1 << 12) - 1; |
| 51 | size += 1; |
| 52 | valid = mask & MTRR_PHYS_MASK_VALID; |
| 53 | type = mtrr_type_name[base & MTRR_BASE_TYPE_MASK]; |
| 54 | printf("%d %-5s %-12s %016llx %016llx %016llx\n", i, |
Bin Meng | 933a29b | 2015-07-06 16:31:32 +0800 | [diff] [blame] | 55 | valid ? "Y" : "N", type, base & ~MTRR_BASE_TYPE_MASK, |
| 56 | mask & ~MTRR_PHYS_MASK_VALID, size); |
Simon Glass | fc0ba2d | 2015-01-01 16:18:15 -0700 | [diff] [blame] | 57 | } |
| 58 | |
| 59 | return 0; |
| 60 | } |
| 61 | |
Simon Glass | 29e1d77 | 2020-07-17 08:48:27 -0600 | [diff] [blame^] | 62 | static int do_mtrr_set(int cpu_select, uint reg, int argc, char *const argv[]) |
Simon Glass | fc0ba2d | 2015-01-01 16:18:15 -0700 | [diff] [blame] | 63 | { |
| 64 | const char *typename = argv[0]; |
Simon Glass | fc0ba2d | 2015-01-01 16:18:15 -0700 | [diff] [blame] | 65 | uint32_t start, size; |
| 66 | uint64_t base, mask; |
| 67 | int i, type = -1; |
| 68 | bool valid; |
Simon Glass | 29e1d77 | 2020-07-17 08:48:27 -0600 | [diff] [blame^] | 69 | int ret; |
Simon Glass | fc0ba2d | 2015-01-01 16:18:15 -0700 | [diff] [blame] | 70 | |
| 71 | if (argc < 3) |
| 72 | return CMD_RET_USAGE; |
| 73 | for (i = 0; i < MTRR_TYPE_COUNT; i++) { |
| 74 | if (*typename == *mtrr_type_name[i]) |
| 75 | type = i; |
| 76 | } |
| 77 | if (type == -1) { |
| 78 | printf("Invalid type name %s\n", typename); |
| 79 | return CMD_RET_USAGE; |
| 80 | } |
| 81 | start = simple_strtoul(argv[1], NULL, 16); |
| 82 | size = simple_strtoul(argv[2], NULL, 16); |
| 83 | |
| 84 | base = start | type; |
| 85 | valid = native_read_msr(MTRR_PHYS_MASK_MSR(reg)) & MTRR_PHYS_MASK_VALID; |
| 86 | mask = ~((uint64_t)size - 1); |
| 87 | mask &= (1ULL << CONFIG_CPU_ADDR_BITS) - 1; |
| 88 | if (valid) |
| 89 | mask |= MTRR_PHYS_MASK_VALID; |
| 90 | |
Simon Glass | 29e1d77 | 2020-07-17 08:48:27 -0600 | [diff] [blame^] | 91 | ret = mtrr_set(cpu_select, reg, base, mask); |
| 92 | if (ret) |
| 93 | return CMD_RET_FAILURE; |
Simon Glass | fc0ba2d | 2015-01-01 16:18:15 -0700 | [diff] [blame] | 94 | |
| 95 | return 0; |
| 96 | } |
| 97 | |
Simon Glass | ed38aef | 2020-05-10 11:40:03 -0600 | [diff] [blame] | 98 | static int do_mtrr(struct cmd_tbl *cmdtp, int flag, int argc, |
| 99 | char *const argv[]) |
Simon Glass | fc0ba2d | 2015-01-01 16:18:15 -0700 | [diff] [blame] | 100 | { |
| 101 | const char *cmd; |
Simon Glass | 7403c26 | 2020-07-17 08:48:22 -0600 | [diff] [blame] | 102 | int cpu_select; |
Simon Glass | fc0ba2d | 2015-01-01 16:18:15 -0700 | [diff] [blame] | 103 | uint reg; |
| 104 | |
Simon Glass | 7403c26 | 2020-07-17 08:48:22 -0600 | [diff] [blame] | 105 | cpu_select = MP_SELECT_BSP; |
Simon Glass | fc0ba2d | 2015-01-01 16:18:15 -0700 | [diff] [blame] | 106 | cmd = argv[1]; |
| 107 | if (argc < 2 || *cmd == 'l') |
Simon Glass | 7403c26 | 2020-07-17 08:48:22 -0600 | [diff] [blame] | 108 | return do_mtrr_list(cpu_select); |
Simon Glass | fc0ba2d | 2015-01-01 16:18:15 -0700 | [diff] [blame] | 109 | argc -= 2; |
| 110 | argv += 2; |
| 111 | if (argc <= 0) |
| 112 | return CMD_RET_USAGE; |
| 113 | reg = simple_strtoul(argv[0], NULL, 16); |
| 114 | if (reg >= MTRR_COUNT) { |
| 115 | printf("Invalid register number\n"); |
| 116 | return CMD_RET_USAGE; |
| 117 | } |
| 118 | if (*cmd == 'e') |
Simon Glass | 29e1d77 | 2020-07-17 08:48:27 -0600 | [diff] [blame^] | 119 | return mtrr_set_valid(cpu_select, reg, true); |
Simon Glass | fc0ba2d | 2015-01-01 16:18:15 -0700 | [diff] [blame] | 120 | else if (*cmd == 'd') |
Simon Glass | 29e1d77 | 2020-07-17 08:48:27 -0600 | [diff] [blame^] | 121 | return mtrr_set_valid(cpu_select, reg, false); |
Simon Glass | fc0ba2d | 2015-01-01 16:18:15 -0700 | [diff] [blame] | 122 | else if (*cmd == 's') |
Simon Glass | 29e1d77 | 2020-07-17 08:48:27 -0600 | [diff] [blame^] | 123 | return do_mtrr_set(cpu_select, reg, argc - 1, argv + 1); |
Simon Glass | fc0ba2d | 2015-01-01 16:18:15 -0700 | [diff] [blame] | 124 | else |
| 125 | return CMD_RET_USAGE; |
| 126 | |
| 127 | return 0; |
| 128 | } |
| 129 | |
| 130 | U_BOOT_CMD( |
| 131 | mtrr, 6, 1, do_mtrr, |
| 132 | "Use x86 memory type range registers (32-bit only)", |
| 133 | "[list] - list current registers\n" |
| 134 | "set <reg> <type> <start> <size> - set a register\n" |
| 135 | "\t<type> is Uncacheable, Combine, Through, Protect, Back\n" |
| 136 | "disable <reg> - disable a register\n" |
Simon Glass | c947a62 | 2020-07-17 08:48:12 -0600 | [diff] [blame] | 137 | "enable <reg> - enable a register" |
Simon Glass | fc0ba2d | 2015-01-01 16:18:15 -0700 | [diff] [blame] | 138 | ); |