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git01.mediatek.com / filogic / uboot / 97ad2935ae00a48e41df6e499250b48845a99ecb / . / configs / evb-px5_defconfig
blob: 82620159ab117683533220fcaf9666e02764239d [file] [log] [blame]
Andy Yanad63aac2017-05-15 17:54:48 +0800[diff] [blame]1CONFIG_ARM=y
Tom Rinie1e85442021-08-27 21:18:30 -0400[diff] [blame]2CONFIG_SKIP_LOWLEVEL_INIT=y
Peng Fanc8a61c02022-04-13 17:47:20 +0800[diff] [blame]3CONFIG_COUNTER_FREQUENCY=24000000
Andy Yanad63aac2017-05-15 17:54:48 +0800[diff] [blame]4CONFIG_ARCH_ROCKCHIP=y
Tom Rini07edfae2018-02-03 12:10:38 -0500[diff] [blame]5CONFIG_SYS_TEXT_BASE=0x00200000
Tom Rini2e262c42020-08-10 15:31:07 -0400[diff] [blame]6CONFIG_NR_DRAM_BANKS=1
Tom Rinif6e6e1a2020-01-22 13:38:00 -0500[diff] [blame]7CONFIG_ENV_OFFSET=0x3F8000
Tom Rinia20e51f2021-06-28 10:17:29 -0400[diff] [blame]8CONFIG_DEFAULT_DEVICE_TREE="rk3368-px5-evb"
Andy Yanad63aac2017-05-15 17:54:48 +0800[diff] [blame]9CONFIG_ROCKCHIP_RK3368=y
Tom Rini28862bf2019-11-21 08:30:45 -0500[diff] [blame]10CONFIG_TPL_LDSCRIPT="arch/arm/mach-rockchip/u-boot-tpl-v8.lds"
Kever Yang38dc38b2019-02-12 15:19:07 +0800[diff] [blame]11CONFIG_TPL_LIBCOMMON_SUPPORT=y
12CONFIG_TPL_LIBGENERIC_SUPPORT=y
Simon Glass284cb9c2021-07-10 21:14:31 -0600[diff] [blame]13CONFIG_SPL_DRIVERS_MISC=y
Andy Yanad63aac2017-05-15 17:54:48 +0800[diff] [blame]14CONFIG_TARGET_EVB_PX5=y
Kever Yang38dc38b2019-02-12 15:19:07 +0800[diff] [blame]15CONFIG_SPL_STACK_R_ADDR=0x600000
16CONFIG_SPL=y
Tom Rinie0056d72018-06-04 11:57:37 -0400[diff] [blame]17CONFIG_DEBUG_UART_BASE=0xFF1c0000
18CONFIG_DEBUG_UART_CLOCK=24000000
Kever Yang38dc38b2019-02-12 15:19:07 +0800[diff] [blame]19CONFIG_SPL_SPI_FLASH_SUPPORT=y
Simon Glassa5820472021-08-08 12:20:14 -0600[diff] [blame]20CONFIG_SPL_SPI=y
Tom Rini0997ee02021-08-23 10:25:31 -0400[diff] [blame]21CONFIG_SYS_LOAD_ADDR=0x800800
Tom Rini4b2fcb32022-04-08 13:36:51 -0400[diff] [blame]22CONFIG_DEBUG_UART=y
Tom Rini4ddbade2022-05-25 12:16:03 -0400[diff] [blame]23CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
24CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000
Tom Rini61c41ac2017-09-08 10:14:49 -0400[diff] [blame]25CONFIG_ANDROID_BOOT_IMAGE=y
Kever Yang38dc38b2019-02-12 15:19:07 +0800[diff] [blame]26CONFIG_FIT=y
27CONFIG_FIT_VERBOSE=y
28CONFIG_SPL_LOAD_FIT=y
Kever Yang38dc38b2019-02-12 15:19:07 +0800[diff] [blame]29CONFIG_BOOTSTAGE=y
30CONFIG_SPL_BOOTSTAGE=y
31CONFIG_BOOTSTAGE_REPORT=y
32CONFIG_BOOTSTAGE_FDT=y
Klaus Goger2b6b4f22018-05-25 23:45:05 +0200[diff] [blame]33CONFIG_DEFAULT_FDT_FILE="rockchip/rk3368-px5-evb.dtb"
Andy Yanad63aac2017-05-15 17:54:48 +0800[diff] [blame]34# CONFIG_DISPLAY_CPUINFO is not set
Mario Sixf7055442018-03-28 14:38:17 +0200[diff] [blame]35CONFIG_DISPLAY_BOARDINFO_LATE=y
Andy Yanad63aac2017-05-15 17:54:48 +0800[diff] [blame]36CONFIG_ARCH_EARLY_INIT_R=y
Tom Riniabb0f522022-05-16 17:20:26 -0400[diff] [blame]37CONFIG_SPL_MAX_SIZE=0x40000
38CONFIG_SPL_PAD_TO=0x7f8000
Tom Rini65aa1242022-05-27 10:19:45 -0400[diff] [blame]39CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
40CONFIG_SPL_BSS_START_ADDR=0x400000
Tom Rini0cb89e72022-05-19 15:09:22 -0400[diff] [blame]41CONFIG_SPL_BSS_MAX_SIZE=0x20000
Kever Yang38dc38b2019-02-12 15:19:07 +0800[diff] [blame]42CONFIG_SPL_BOOTROM_SUPPORT=y
Kever Yang69a74a52019-08-20 11:47:01 +0800[diff] [blame]43# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
Kever Yang38dc38b2019-02-12 15:19:07 +0800[diff] [blame]44CONFIG_TPL_SYS_MALLOC_SIMPLE=y
Tom Rini8a14ac42022-05-26 13:13:21 -0400[diff] [blame]45# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
46CONFIG_SPL_STACK=0x188000
Kever Yang38dc38b2019-02-12 15:19:07 +0800[diff] [blame]47CONFIG_SPL_STACK_R=y
48CONFIG_SPL_ATF=y
49CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
50CONFIG_TPL=y
Tom Riniabb0f522022-05-16 17:20:26 -0400[diff] [blame]51CONFIG_TPL_MAX_SIZE=0x40000
Andy Yanad63aac2017-05-15 17:54:48 +0800[diff] [blame]52CONFIG_CMD_MMC=y
53CONFIG_CMD_CACHE=y
Kever Yang38dc38b2019-02-12 15:19:07 +0800[diff] [blame]54CONFIG_SPL_OF_CONTROL=y
55CONFIG_TPL_OF_CONTROL=y
56CONFIG_OF_LIVE=y
Kever Yang38dc38b2019-02-12 15:19:07 +0800[diff] [blame]57CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names interrupt-parent"
58CONFIG_TPL_OF_PLATDATA=y
59CONFIG_ENV_IS_IN_MMC=y
Tom Rinica63e712019-11-12 22:46:36 -0500[diff] [blame]60CONFIG_SYS_RELOC_GD_ENV_ADDR=y
Andy Yanfbe7d702019-11-26 21:15:40 +0800[diff] [blame]61# CONFIG_NET is not set
Kever Yang38dc38b2019-02-12 15:19:07 +0800[diff] [blame]62CONFIG_TPL_DM=y
Andy Yanad63aac2017-05-15 17:54:48 +0800[diff] [blame]63CONFIG_REGMAP=y
Kever Yang38dc38b2019-02-12 15:19:07 +0800[diff] [blame]64CONFIG_SPL_REGMAP=y
65CONFIG_TPL_REGMAP=y
Andy Yanad63aac2017-05-15 17:54:48 +0800[diff] [blame]66CONFIG_SYSCON=y
Kever Yang38dc38b2019-02-12 15:19:07 +0800[diff] [blame]67CONFIG_SPL_SYSCON=y
68CONFIG_TPL_SYSCON=y
Andy Yanad63aac2017-05-15 17:54:48 +0800[diff] [blame]69CONFIG_CLK=y
Kever Yang38dc38b2019-02-12 15:19:07 +0800[diff] [blame]70CONFIG_SPL_CLK=y
71CONFIG_TPL_CLK=y
Andy Yanad63aac2017-05-15 17:54:48 +0800[diff] [blame]72CONFIG_MMC_DW=y
73CONFIG_MMC_DW_ROCKCHIP=y
74CONFIG_PINCTRL=y
Kever Yang38dc38b2019-02-12 15:19:07 +0800[diff] [blame]75CONFIG_SPL_PINCTRL=y
Andy Yanad63aac2017-05-15 17:54:48 +0800[diff] [blame]76CONFIG_RAM=y
Kever Yang38dc38b2019-02-12 15:19:07 +0800[diff] [blame]77CONFIG_SPL_RAM=y
78CONFIG_TPL_RAM=y
79CONFIG_DM_RESET=y
Andy Yanad63aac2017-05-15 17:54:48 +0800[diff] [blame]80CONFIG_DEBUG_UART_SHIFT=2
Andy Yanad63aac2017-05-15 17:54:48 +0800[diff] [blame]81CONFIG_DEBUG_UART_SKIP_INIT=y
82CONFIG_SYSRESET=y
Kever Yang38dc38b2019-02-12 15:19:07 +0800[diff] [blame]83CONFIG_PANIC_HANG=y
84CONFIG_SPL_TINY_MEMSET=y
85CONFIG_TPL_TINY_MEMSET=y
Andy Yanad63aac2017-05-15 17:54:48 +0800[diff] [blame]86CONFIG_ERRNO_STR=y