blob: 44c9b50fe5b84d5a140c4d10c6bd91e8f78fa25c [file] [log] [blame]
Michal Simekeb1dfa72013-02-04 12:38:59 +01001/*
2 * Copyright (c) 2013 Xilinx Inc.
3 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02004 * SPDX-License-Identifier: GPL-2.0+
Michal Simekeb1dfa72013-02-04 12:38:59 +01005 */
6
7#ifndef _SYS_PROTO_H_
8#define _SYS_PROTO_H_
9
10extern void zynq_slcr_lock(void);
11extern void zynq_slcr_unlock(void);
12extern void zynq_slcr_cpu_reset(void);
Soren Brinkmann4dded982013-11-21 13:39:01 -080013extern void zynq_slcr_gem_clk_setup(u32 gem_id, unsigned long clk_rate);
Michal Simek15d654c2013-04-22 15:43:02 +020014extern void zynq_slcr_devcfg_disable(void);
15extern void zynq_slcr_devcfg_enable(void);
Jagannadha Sutradharudu Teki11704c22014-01-09 01:48:21 +053016extern u32 zynq_slcr_get_boot_mode(void);
Michal Simek15d654c2013-04-22 15:43:02 +020017extern u32 zynq_slcr_get_idcode(void);
Michal Simek8d191622014-04-25 12:21:04 +020018extern int zynq_slcr_get_mio_pin_status(const char *periph);
Michal Simekf5ff7bc2013-06-17 14:37:01 +020019extern void zynq_ddrc_init(void);
Siva Durga Prasad Paladugue26ef3b2013-11-29 19:01:25 +053020extern unsigned int zynq_get_silicon_version(void);
Michal Simekeb1dfa72013-02-04 12:38:59 +010021
Joe Hershberger7f4e5552016-01-26 11:57:03 -060022int zynq_board_read_rom_ethaddr(unsigned char *ethaddr);
23
Michal Simek0dd222b2013-04-22 14:56:49 +020024/* Driver extern functions */
Michal Simekbf4b1492014-08-11 14:01:57 +020025extern void ps7_init(void);
26
Michal Simekeb1dfa72013-02-04 12:38:59 +010027#endif /* _SYS_PROTO_H_ */