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git01.mediatek.com / filogic / uboot / 2c2395d4a4bfd7261c920b0b1e4ffc2350b57c63 / . / arch / arm / dts / imx8mp-verdin-wifi-dev-u-boot.dtsi
blob: 2a1aa1935a76ab48eaed0ceba59e4d9c7ce51906 [file] [log] [blame]
Marcel Ziswiler36a439d2022-02-07 11:54:13 +0100[diff] [blame]1// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2/*
3 * Copyright 2022 Toradex
4 */
5
6#include "imx8mp-u-boot.dtsi"
7
8/ {
Marcel Ziswiler36a439d2022-02-07 11:54:13 +0100[diff] [blame]9 wdt-reboot {
10 compatible = "wdt-reboot";
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]11 bootph-pre-ram;
Marcel Ziswiler36a439d2022-02-07 11:54:13 +0100[diff] [blame]12 wdt = <&wdog1>;
13 };
14};
15
Marcel Ziswilerf8621462022-07-21 15:46:44 +0200[diff] [blame]16&{/aliases} {
17 eeprom0 = &eeprom_module;
18 eeprom1 = &eeprom_carrier_board;
19 eeprom2 = &eeprom_display_adapter;
20};
21
Marcel Ziswiler36a439d2022-02-07 11:54:13 +0100[diff] [blame]22&clk {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]23 bootph-all;
24 bootph-pre-ram;
Marcel Ziswiler36a439d2022-02-07 11:54:13 +0100[diff] [blame]25 /delete-property/ assigned-clocks;
26 /delete-property/ assigned-clock-parents;
27 /delete-property/ assigned-clock-rates;
28
29};
30
Marcel Ziswiler36a439d2022-02-07 11:54:13 +0100[diff] [blame]31&gpio1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]32 bootph-pre-ram;
Marcel Ziswiler36a439d2022-02-07 11:54:13 +0100[diff] [blame]33};
34
35&gpio2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]36 bootph-pre-ram;
Marcel Ziswilerf8621462022-07-21 15:46:44 +0200[diff] [blame]37
38 regulator-ethphy {
39 gpio-hog;
40 gpios = <20 GPIO_ACTIVE_HIGH>;
41 line-name = "reg_ethphy";
42 output-high;
43 pinctrl-names = "default";
44 pinctrl-0 = <&pinctrl_reg_eth>;
45 };
Marcel Ziswiler36a439d2022-02-07 11:54:13 +0100[diff] [blame]46};
47
48&gpio3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]49 bootph-pre-ram;
Marcel Ziswiler36a439d2022-02-07 11:54:13 +0100[diff] [blame]50};
51
52&gpio4 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]53 bootph-pre-ram;
Andrejs Cainikovsdd1587c2023-07-11 11:09:18 +0200[diff] [blame]54
55 ctrl-sleep-moci-hog {
56 bootph-pre-ram;
57 };
Marcel Ziswiler36a439d2022-02-07 11:54:13 +0100[diff] [blame]58};
59
60&gpio5 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]61 bootph-pre-ram;
Marcel Ziswiler36a439d2022-02-07 11:54:13 +0100[diff] [blame]62};
63
64&i2c1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]65 bootph-pre-ram;
Marcel Ziswilerf8621462022-07-21 15:46:44 +0200[diff] [blame]66
67 eeprom_module: eeprom@50 {
68 compatible = "i2c-eeprom";
69 pagesize = <16>;
70 reg = <0x50>;
71 };
Marcel Ziswiler36a439d2022-02-07 11:54:13 +0100[diff] [blame]72};
73
74&i2c2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]75 bootph-pre-ram;
Marcel Ziswiler36a439d2022-02-07 11:54:13 +0100[diff] [blame]76};
77
78&i2c3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]79 bootph-pre-ram;
Marcel Ziswiler36a439d2022-02-07 11:54:13 +0100[diff] [blame]80};
81
Marcel Ziswilerf8621462022-07-21 15:46:44 +0200[diff] [blame]82&i2c4 {
83 /* EEPROM on display adapter (MIPI DSI Display Adapter) */
84 eeprom_display_adapter: eeprom@50 {
85 compatible = "i2c-eeprom";
86 pagesize = <16>;
87 reg = <0x50>;
88 };
89
90 /* EEPROM on carrier board */
91 eeprom_carrier_board: eeprom@57 {
92 compatible = "i2c-eeprom";
93 pagesize = <16>;
94 reg = <0x57>;
95 };
96};
97
98&pca9450 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]99 bootph-pre-ram;
Marcel Ziswilerf8621462022-07-21 15:46:44 +0200[diff] [blame]100};
101
Andrejs Cainikovsdd1587c2023-07-11 11:09:18 +0200[diff] [blame]102&pinctrl_ctrl_sleep_moci {
103 bootph-pre-ram;
104};
105
Marcel Ziswiler36a439d2022-02-07 11:54:13 +0100[diff] [blame]106&pinctrl_i2c1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]107 bootph-pre-ram;
Marcel Ziswiler36a439d2022-02-07 11:54:13 +0100[diff] [blame]108};
109
Marcel Ziswilerf8621462022-07-21 15:46:44 +0200[diff] [blame]110&pinctrl_usdhc2_pwr_en {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]111 bootph-pre-ram;
Marcel Ziswiler36a439d2022-02-07 11:54:13 +0100[diff] [blame]112 u-boot,off-on-delay-us = <20000>;
113};
114
115&pinctrl_uart3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]116 bootph-pre-ram;
Marcel Ziswiler36a439d2022-02-07 11:54:13 +0100[diff] [blame]117};
118
Marcel Ziswilerf8621462022-07-21 15:46:44 +0200[diff] [blame]119&pinctrl_usdhc2_cd {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]120 bootph-pre-ram;
Marcel Ziswiler36a439d2022-02-07 11:54:13 +0100[diff] [blame]121};
122
123&pinctrl_usdhc2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]124 bootph-pre-ram;
Marcel Ziswiler36a439d2022-02-07 11:54:13 +0100[diff] [blame]125};
126
127&pinctrl_usdhc3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]128 bootph-pre-ram;
Marcel Ziswiler36a439d2022-02-07 11:54:13 +0100[diff] [blame]129};
130
131&pinctrl_wdog {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]132 bootph-pre-ram;
Marcel Ziswiler36a439d2022-02-07 11:54:13 +0100[diff] [blame]133};
134
Marcel Ziswiler36a439d2022-02-07 11:54:13 +0100[diff] [blame]135&reg_usdhc2_vmmc {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]136 bootph-pre-ram;
Marcel Ziswiler36a439d2022-02-07 11:54:13 +0100[diff] [blame]137};
138
139&uart3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]140 bootph-pre-ram;
Marcel Ziswiler36a439d2022-02-07 11:54:13 +0100[diff] [blame]141};
142
Marcel Ziswilerf8621462022-07-21 15:46:44 +0200[diff] [blame]143&usdhc1 {
144 status = "disabled";
145};
146
Marcel Ziswiler36a439d2022-02-07 11:54:13 +0100[diff] [blame]147&usdhc2 {
148 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_400M>;
149 assigned-clock-rates = <400000000>;
150 assigned-clocks = <&clk IMX8MP_CLK_USDHC2>;
151 sd-uhs-ddr50;
152 sd-uhs-sdr104;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]153 bootph-pre-ram;
Marcel Ziswiler36a439d2022-02-07 11:54:13 +0100[diff] [blame]154};
155
156&usdhc3 {
157 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_400M>;
158 assigned-clock-rates = <400000000>;
159 assigned-clocks = <&clk IMX8MP_CLK_USDHC3>;
160 mmc-hs400-1_8v;
161 mmc-hs400-enhanced-strobe;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]162 bootph-pre-ram;
Marcel Ziswiler36a439d2022-02-07 11:54:13 +0100[diff] [blame]163};
164
165&wdog1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]166 bootph-pre-ram;
Marcel Ziswiler36a439d2022-02-07 11:54:13 +0100[diff] [blame]167};