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git01.mediatek.com / filogic / uboot / 2c2395d4a4bfd7261c920b0b1e4ffc2350b57c63 / . / arch / arm / dts / imx8mp-venice-gw72xx.dtsi
blob: 4e726128ccfc8a69726831b6f0d9de0f0a01f9d3 [file] [log] [blame]
Tim Harvey7e0bfc62023-08-15 15:01:12 -0700[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright 2023 Gateworks Corporation
4 */
5
6#include <dt-bindings/gpio/gpio.h>
7#include <dt-bindings/leds/common.h>
8#include <dt-bindings/phy/phy-imx8-pcie.h>
9
10/ {
11 led-controller {
12 compatible = "gpio-leds";
13 pinctrl-names = "default";
14 pinctrl-0 = <&pinctrl_gpio_leds>;
15
16 led-0 {
17 function = LED_FUNCTION_STATUS;
18 color = <LED_COLOR_ID_GREEN>;
19 gpios = <&gpio4 1 GPIO_ACTIVE_HIGH>;
20 default-state = "on";
21 linux,default-trigger = "heartbeat";
22 };
23
24 led-1 {
25 function = LED_FUNCTION_STATUS;
26 color = <LED_COLOR_ID_RED>;
27 gpios = <&gpio4 5 GPIO_ACTIVE_HIGH>;
28 default-state = "off";
29 };
30 };
31
32 pcie0_refclk: pcie0-refclk {
33 compatible = "fixed-clock";
34 #clock-cells = <0>;
35 clock-frequency = <100000000>;
36 };
37
38 pps {
39 compatible = "pps-gpio";
40 pinctrl-names = "default";
41 pinctrl-0 = <&pinctrl_pps>;
42 gpios = <&gpio4 3 GPIO_ACTIVE_HIGH>;
43 status = "okay";
44 };
45
46 reg_usb1_vbus: regulator-usb1 {
47 pinctrl-names = "default";
48 pinctrl-0 = <&pinctrl_reg_usb1_en>;
49 compatible = "regulator-fixed";
50 regulator-name = "usb1_vbus";
51 gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
52 enable-active-high;
53 regulator-min-microvolt = <5000000>;
54 regulator-max-microvolt = <5000000>;
55 };
56
57 reg_usb2_vbus: regulator-usb2 {
58 pinctrl-names = "default";
59 pinctrl-0 = <&pinctrl_reg_usb2_en>;
60 compatible = "regulator-fixed";
61 regulator-name = "usb2_vbus";
62 gpio = <&gpio4 12 GPIO_ACTIVE_HIGH>;
63 enable-active-high;
64 regulator-min-microvolt = <5000000>;
65 regulator-max-microvolt = <5000000>;
66 };
67
68 reg_usdhc2_vmmc: regulator-usdhc2-vmmc {
69 pinctrl-names = "default";
70 pinctrl-0 = <&pinctrl_usdhc2_vmmc>;
71 compatible = "regulator-fixed";
72 regulator-name = "VDD_3V3_SD";
73 enable-active-high;
74 gpio = <&gpio2 19 0>; /* SD2_RESET */
75 off-on-delay-us = <12000>;
76 regulator-max-microvolt = <3300000>;
77 regulator-min-microvolt = <3300000>;
78 startup-delay-us = <100>;
79 };
80};
81
82/* off-board header */
83&ecspi2 {
84 pinctrl-names = "default";
85 pinctrl-0 = <&pinctrl_spi2>;
Tim Harvey18b5d7d2023-11-27 11:37:23 -0800[diff] [blame]86 cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>,
87 <&gpio1 10 GPIO_ACTIVE_LOW>;
Tim Harvey7e0bfc62023-08-15 15:01:12 -0700[diff] [blame]88 status = "okay";
Tim Harvey18b5d7d2023-11-27 11:37:23 -0800[diff] [blame]89 tpm@1 {
90 compatible = "tcg,tpm_tis-spi";
91 reg = <0x1>;
92 spi-max-frequency = <36000000>;
93 };
Tim Harvey7e0bfc62023-08-15 15:01:12 -0700[diff] [blame]94};
95
96&gpio4 {
97 gpio-line-names =
98 "", "", "", "",
99 "", "", "", "",
100 "dio1", "", "", "dio0",
101 "", "", "pci_usb_sel", "",
102 "", "", "", "",
103 "", "", "rs485_en", "rs485_term",
104 "", "", "", "rs485_half",
105 "pci_wdis#", "", "", "";
106};
107
108&i2c2 {
109 clock-frequency = <400000>;
110 pinctrl-names = "default";
111 pinctrl-0 = <&pinctrl_i2c2>;
112 status = "okay";
113
114 accelerometer@19 {
115 pinctrl-names = "default";
116 pinctrl-0 = <&pinctrl_accel>;
117 compatible = "st,lis2de12";
118 reg = <0x19>;
119 st,drdy-int-pin = <1>;
120 interrupt-parent = <&gpio4>;
121 interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
122 interrupt-names = "INT1";
123 };
124};
125
126&pcie_phy {
127 fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
128 fsl,clkreq-unsupported;
129 clocks = <&pcie0_refclk>;
130 clock-names = "ref";
131 status = "okay";
132};
133
134&pcie {
135 pinctrl-names = "default";
136 pinctrl-0 = <&pinctrl_pcie0>;
137 reset-gpio = <&gpio4 29 GPIO_ACTIVE_LOW>;
138 status = "okay";
139};
140
141/* GPS */
142&uart1 {
143 pinctrl-names = "default";
144 pinctrl-0 = <&pinctrl_uart1>;
145 status = "okay";
146};
147
148/* off-board header */
149&uart3 {
150 pinctrl-names = "default";
151 pinctrl-0 = <&pinctrl_uart3>;
152 status = "okay";
153};
154
155/* RS232 */
156&uart4 {
157 pinctrl-names = "default";
158 pinctrl-0 = <&pinctrl_uart4>;
159 status = "okay";
160};
161
162/* USB1 - OTG */
163&usb3_0 {
164 pinctrl-names = "default";
165 pinctrl-0 = <&pinctrl_usb1>;
166 fsl,over-current-active-low;
167 status = "okay";
168};
169
170&usb3_phy0 {
171 vbus-supply = <&reg_usb1_vbus>;
172 status = "okay";
173};
174
175&usb_dwc3_0 {
176 /* dual role is implemented but not a full featured OTG */
177 adp-disable;
178 hnp-disable;
179 srp-disable;
180 dr_mode = "otg";
181 usb-role-switch;
182 role-switch-default-mode = "peripheral";
183 status = "okay";
184
185 connector {
186 pinctrl-names = "default";
187 pinctrl-0 = <&pinctrl_usbcon1>;
188 compatible = "gpio-usb-b-connector", "usb-b-connector";
189 type = "micro";
190 label = "otg";
191 id-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>;
192 };
193};
194
195/* USB2 - USB3.0 Hub */
196&usb3_1 {
197 fsl,permanently-attached;
198 fsl,disable-port-power-control;
199 status = "okay";
200};
201
202&usb3_phy1 {
203 vbus-supply = <&reg_usb2_vbus>;
204 status = "okay";
205};
206
207&usb_dwc3_1 {
208 dr_mode = "host";
209 status = "okay";
210};
211
212/* microSD */
213&usdhc2 {
214 pinctrl-names = "default", "state_100mhz", "state_200mhz";
215 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
216 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
217 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
218 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
219 bus-width = <4>;
220 vmmc-supply = <&reg_usdhc2_vmmc>;
221 status = "okay";
222};
223
224&iomuxc {
225 pinctrl-names = "default";
226 pinctrl-0 = <&pinctrl_hog>;
227
228 pinctrl_hog: hoggrp {
229 fsl,pins = <
230 MX8MP_IOMUXC_SAI1_RXD6__GPIO4_IO08 0x40000146 /* DIO1 */
231 MX8MP_IOMUXC_SAI1_TXC__GPIO4_IO11 0x40000146 /* DIO0 */
232 MX8MP_IOMUXC_SAI1_TXD2__GPIO4_IO14 0x40000106 /* PCIE_USBSEL */
233 MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x40000106 /* RS485_HALF */
234 MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x40000106 /* RS485_EN */
235 MX8MP_IOMUXC_SAI2_RXD0__GPIO4_IO23 0x40000106 /* RS485_TERM */
236 MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x40000106 /* PCIE_WDIS# */
237 >;
238 };
239
240 pinctrl_accel: accelgrp {
241 fsl,pins = <
242 MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21 0x150 /* IRQ */
243 >;
244 };
245
246 pinctrl_gpio_leds: gpioledgrp {
247 fsl,pins = <
248 MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01 0x6 /* LEDG */
249 MX8MP_IOMUXC_SAI1_RXD3__GPIO4_IO05 0x6 /* LEDR */
250 >;
251 };
252
253 pinctrl_pcie0: pcie0grp {
254 fsl,pins = <
255 MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x106
256 >;
257 };
258
259 pinctrl_pps: ppsgrp {
260 fsl,pins = <
261 MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03 0x146
262 >;
263 };
264
265 pinctrl_reg_usb1_en: regusb1grp {
266 fsl,pins = <
267 MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x146 /* USB1_EN */
268 >;
269 };
270
271 pinctrl_usb1: usb1grp {
272 fsl,pins = <
273 MX8MP_IOMUXC_GPIO1_IO13__USB1_OTG_OC 0x140 /* USB1_FLT# */
274 >;
275 };
276
277 pinctrl_usbcon1: usbcon1grp {
278 fsl,pins = <
279 MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21 0x140 /* USB1_ID */
280 >;
281 };
282
283 pinctrl_reg_usb2_en: regusb2grp {
284 fsl,pins = <
285 MX8MP_IOMUXC_SAI1_TXD0__GPIO4_IO12 0x146 /* USBHUB_RST# */
286 >;
287 };
288
289 pinctrl_spi2: spi2grp {
290 fsl,pins = <
291 MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x140
292 MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x140
293 MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x140
294 MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x140
Tim Harvey18b5d7d2023-11-27 11:37:23 -0800[diff] [blame]295 MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x140
Tim Harvey7e0bfc62023-08-15 15:01:12 -0700[diff] [blame]296 >;
297 };
298
299 pinctrl_uart1: uart1grp {
300 fsl,pins = <
301 MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140
302 MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140
303 >;
304 };
305
306 pinctrl_uart3: uart3grp {
307 fsl,pins = <
308 MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX 0x140
309 MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX 0x140
310 >;
311 };
312
313 pinctrl_uart4: uart4grp {
314 fsl,pins = <
315 MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x140
316 MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x140
317 >;
318 };
319
320 pinctrl_usdhc1: usdhc1grp {
321 fsl,pins = <
322 MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190
323 MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0
324 MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0
325 MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0
326 MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0
327 MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0
328 >;
329 };
330
331 pinctrl_usdhc2: usdhc2grp {
332 fsl,pins = <
333 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190
334 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0
335 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0
336 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0
337 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0
338 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0
339 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
340 >;
341 };
342
343 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
344 fsl,pins = <
345 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194
346 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4
347 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4
348 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4
349 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4
350 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4
351 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
352 >;
353 };
354
355 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
356 fsl,pins = <
357 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196
358 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6
359 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6
360 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6
361 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6
362 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6
363 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
364 >;
365 };
366
367 pinctrl_usdhc2_vmmc: usdhc2-vmmc-grp {
368 fsl,pins = <
369 MX8MP_IOMUXC_SD2_RESET_B__USDHC2_RESET_B 0x1d0
370 >;
371 };
372
373 pinctrl_usdhc2_gpio: usdhc2gpiogrp {
374 fsl,pins = <
375 MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4
376 >;
377 };
378};