Tien Fong Chee | 1d675f3 | 2017-07-26 13:05:43 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2017 Intel Corporation <www.intel.com> |
| 3 | * |
| 4 | * SPDX-License-Identifier: GPL-2.0 |
| 5 | */ |
| 6 | |
| 7 | #include <asm/io.h> |
| 8 | #include <asm/arch/fpga_manager.h> |
| 9 | #include <asm/arch/reset_manager.h> |
| 10 | #include <asm/arch/system_manager.h> |
| 11 | #include <asm/arch/sdram.h> |
| 12 | #include <asm/arch/misc.h> |
| 13 | #include <altera.h> |
| 14 | #include <common.h> |
| 15 | #include <errno.h> |
| 16 | #include <wait_bit.h> |
| 17 | #include <watchdog.h> |
| 18 | |
| 19 | #define CFGWDTH_32 1 |
| 20 | #define MIN_BITSTREAM_SIZECHECK 230 |
| 21 | #define ENCRYPTION_OFFSET 69 |
| 22 | #define COMPRESSION_OFFSET 229 |
| 23 | #define FPGA_TIMEOUT_MSEC 1000 /* timeout in ms */ |
| 24 | #define FPGA_TIMEOUT_CNT 0x1000000 |
| 25 | |
| 26 | DECLARE_GLOBAL_DATA_PTR; |
| 27 | |
| 28 | static const struct socfpga_fpga_manager *fpga_manager_base = |
| 29 | (void *)SOCFPGA_FPGAMGRREGS_ADDRESS; |
| 30 | |
| 31 | static const struct socfpga_system_manager *system_manager_base = |
| 32 | (void *)SOCFPGA_SYSMGR_ADDRESS; |
| 33 | |
| 34 | static void fpgamgr_set_cd_ratio(unsigned long ratio); |
| 35 | |
| 36 | static uint32_t fpgamgr_get_msel(void) |
| 37 | { |
| 38 | u32 reg; |
| 39 | |
| 40 | reg = readl(&fpga_manager_base->imgcfg_stat); |
| 41 | reg = (reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL_SET_MSD) >> |
| 42 | ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL0_LSB; |
| 43 | |
| 44 | return reg; |
| 45 | } |
| 46 | |
| 47 | static void fpgamgr_set_cfgwdth(int width) |
| 48 | { |
| 49 | if (width) |
| 50 | setbits_le32(&fpga_manager_base->imgcfg_ctrl_02, |
| 51 | ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_SET_MSK); |
| 52 | else |
| 53 | clrbits_le32(&fpga_manager_base->imgcfg_ctrl_02, |
| 54 | ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_SET_MSK); |
| 55 | } |
| 56 | |
| 57 | int is_fpgamgr_user_mode(void) |
| 58 | { |
| 59 | return (readl(&fpga_manager_base->imgcfg_stat) & |
| 60 | ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK) != 0; |
| 61 | } |
| 62 | |
| 63 | static int wait_for_user_mode(void) |
| 64 | { |
Álvaro Fernández Rojas | 918de03 | 2018-01-23 17:14:55 +0100 | [diff] [blame] | 65 | return wait_for_bit_le32(&fpga_manager_base->imgcfg_stat, |
Tien Fong Chee | 1d675f3 | 2017-07-26 13:05:43 +0800 | [diff] [blame] | 66 | ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK, |
| 67 | 1, FPGA_TIMEOUT_MSEC, false); |
| 68 | } |
| 69 | |
| 70 | static int is_fpgamgr_early_user_mode(void) |
| 71 | { |
| 72 | return (readl(&fpga_manager_base->imgcfg_stat) & |
| 73 | ALT_FPGAMGR_IMGCFG_STAT_F2S_EARLY_USERMODE_SET_MSK) != 0; |
| 74 | } |
| 75 | |
| 76 | int fpgamgr_wait_early_user_mode(void) |
| 77 | { |
| 78 | u32 sync_data = 0xffffffff; |
| 79 | u32 i = 0; |
| 80 | unsigned start = get_timer(0); |
| 81 | unsigned long cd_ratio; |
| 82 | |
| 83 | /* Getting existing CDRATIO */ |
| 84 | cd_ratio = (readl(&fpga_manager_base->imgcfg_ctrl_02) & |
| 85 | ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_SET_MSK) >> |
| 86 | ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_LSB; |
| 87 | |
| 88 | /* Using CDRATIO_X1 for better compatibility */ |
| 89 | fpgamgr_set_cd_ratio(CDRATIO_x1); |
| 90 | |
| 91 | while (!is_fpgamgr_early_user_mode()) { |
| 92 | if (get_timer(start) > FPGA_TIMEOUT_MSEC) |
| 93 | return -ETIMEDOUT; |
| 94 | fpgamgr_program_write((const long unsigned int *)&sync_data, |
| 95 | sizeof(sync_data)); |
| 96 | udelay(FPGA_TIMEOUT_MSEC); |
| 97 | i++; |
| 98 | } |
| 99 | |
| 100 | debug("Additional %i sync word needed\n", i); |
| 101 | |
| 102 | /* restoring original CDRATIO */ |
| 103 | fpgamgr_set_cd_ratio(cd_ratio); |
| 104 | |
| 105 | return 0; |
| 106 | } |
| 107 | |
| 108 | /* Read f2s_nconfig_pin and f2s_nstatus_pin; loop until de-asserted */ |
| 109 | static int wait_for_nconfig_pin_and_nstatus_pin(void) |
| 110 | { |
| 111 | unsigned long mask = ALT_FPGAMGR_IMGCFG_STAT_F2S_NCONFIG_PIN_SET_MSK | |
| 112 | ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK; |
| 113 | |
Tien Fong Chee | 2c0f3ae | 2017-12-05 15:57:58 +0800 | [diff] [blame^] | 114 | /* |
| 115 | * Poll until f2s_nconfig_pin and f2s_nstatus_pin; loop until |
| 116 | * de-asserted, timeout at 1000ms |
Tien Fong Chee | 1d675f3 | 2017-07-26 13:05:43 +0800 | [diff] [blame] | 117 | */ |
Tien Fong Chee | 2c0f3ae | 2017-12-05 15:57:58 +0800 | [diff] [blame^] | 118 | return wait_for_bit_le32(&fpga_manager_base->imgcfg_stat, mask, |
| 119 | true, FPGA_TIMEOUT_MSEC, false); |
Tien Fong Chee | 1d675f3 | 2017-07-26 13:05:43 +0800 | [diff] [blame] | 120 | } |
| 121 | |
| 122 | static int wait_for_f2s_nstatus_pin(unsigned long value) |
| 123 | { |
| 124 | /* Poll until f2s to specific value, timeout at 1000ms */ |
Álvaro Fernández Rojas | 918de03 | 2018-01-23 17:14:55 +0100 | [diff] [blame] | 125 | return wait_for_bit_le32(&fpga_manager_base->imgcfg_stat, |
| 126 | ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK, |
| 127 | value, FPGA_TIMEOUT_MSEC, false); |
Tien Fong Chee | 1d675f3 | 2017-07-26 13:05:43 +0800 | [diff] [blame] | 128 | } |
| 129 | |
| 130 | /* set CD ratio */ |
| 131 | static void fpgamgr_set_cd_ratio(unsigned long ratio) |
| 132 | { |
| 133 | clrbits_le32(&fpga_manager_base->imgcfg_ctrl_02, |
| 134 | ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_SET_MSK); |
| 135 | |
| 136 | setbits_le32(&fpga_manager_base->imgcfg_ctrl_02, |
| 137 | (ratio << ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_LSB) & |
| 138 | ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_SET_MSK); |
| 139 | } |
| 140 | |
| 141 | /* get the MSEL value, verify we are set for FPP configuration mode */ |
| 142 | static int fpgamgr_verify_msel(void) |
| 143 | { |
| 144 | u32 msel = fpgamgr_get_msel(); |
| 145 | |
| 146 | if (msel & ~BIT(0)) { |
| 147 | printf("Fail: read msel=%d\n", msel); |
| 148 | return -EPERM; |
| 149 | } |
| 150 | |
| 151 | return 0; |
| 152 | } |
| 153 | |
| 154 | /* |
| 155 | * Write cdratio and cdwidth based on whether the bitstream is compressed |
| 156 | * and/or encoded |
| 157 | */ |
| 158 | static int fpgamgr_set_cdratio_cdwidth(unsigned int cfg_width, u32 *rbf_data, |
| 159 | size_t rbf_size) |
| 160 | { |
| 161 | unsigned int cd_ratio; |
| 162 | bool encrypt, compress; |
| 163 | |
| 164 | /* |
| 165 | * According to the bitstream specification, |
| 166 | * both encryption and compression status are |
| 167 | * in location before offset 230 of the buffer. |
| 168 | */ |
| 169 | if (rbf_size < MIN_BITSTREAM_SIZECHECK) |
| 170 | return -EINVAL; |
| 171 | |
| 172 | encrypt = (rbf_data[ENCRYPTION_OFFSET] >> 2) & 3; |
| 173 | encrypt = encrypt != 0; |
| 174 | |
| 175 | compress = (rbf_data[COMPRESSION_OFFSET] >> 1) & 1; |
| 176 | compress = !compress; |
| 177 | |
| 178 | debug("header word %d = %08x\n", 69, rbf_data[69]); |
| 179 | debug("header word %d = %08x\n", 229, rbf_data[229]); |
| 180 | debug("read from rbf header: encrypt=%d compress=%d\n", encrypt, compress); |
| 181 | |
| 182 | /* |
| 183 | * from the register map description of cdratio in imgcfg_ctrl_02: |
| 184 | * Normal Configuration : 32bit Passive Parallel |
| 185 | * Partial Reconfiguration : 16bit Passive Parallel |
| 186 | */ |
| 187 | |
| 188 | /* |
| 189 | * cd ratio is dependent on cfg width and whether the bitstream |
| 190 | * is encrypted and/or compressed. |
| 191 | * |
| 192 | * | width | encr. | compr. | cd ratio | |
| 193 | * | 16 | 0 | 0 | 1 | |
| 194 | * | 16 | 0 | 1 | 4 | |
| 195 | * | 16 | 1 | 0 | 2 | |
| 196 | * | 16 | 1 | 1 | 4 | |
| 197 | * | 32 | 0 | 0 | 1 | |
| 198 | * | 32 | 0 | 1 | 8 | |
| 199 | * | 32 | 1 | 0 | 4 | |
| 200 | * | 32 | 1 | 1 | 8 | |
| 201 | */ |
| 202 | if (!compress && !encrypt) { |
| 203 | cd_ratio = CDRATIO_x1; |
| 204 | } else { |
| 205 | if (compress) |
| 206 | cd_ratio = CDRATIO_x4; |
| 207 | else |
| 208 | cd_ratio = CDRATIO_x2; |
| 209 | |
| 210 | /* if 32 bit, double the cd ratio (so register |
| 211 | field setting is incremented) */ |
| 212 | if (cfg_width == CFGWDTH_32) |
| 213 | cd_ratio += 1; |
| 214 | } |
| 215 | |
| 216 | fpgamgr_set_cfgwdth(cfg_width); |
| 217 | fpgamgr_set_cd_ratio(cd_ratio); |
| 218 | |
| 219 | return 0; |
| 220 | } |
| 221 | |
| 222 | static int fpgamgr_reset(void) |
| 223 | { |
| 224 | unsigned long reg; |
| 225 | |
| 226 | /* S2F_NCONFIG = 0 */ |
| 227 | clrbits_le32(&fpga_manager_base->imgcfg_ctrl_00, |
| 228 | ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NCONFIG_SET_MSK); |
| 229 | |
| 230 | /* Wait for f2s_nstatus == 0 */ |
| 231 | if (wait_for_f2s_nstatus_pin(0)) |
| 232 | return -ETIME; |
| 233 | |
| 234 | /* S2F_NCONFIG = 1 */ |
| 235 | setbits_le32(&fpga_manager_base->imgcfg_ctrl_00, |
| 236 | ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NCONFIG_SET_MSK); |
| 237 | |
| 238 | /* Wait for f2s_nstatus == 1 */ |
| 239 | if (wait_for_f2s_nstatus_pin(1)) |
| 240 | return -ETIME; |
| 241 | |
| 242 | /* read and confirm f2s_condone_pin = 0 and f2s_condone_oe = 1 */ |
| 243 | reg = readl(&fpga_manager_base->imgcfg_stat); |
| 244 | if ((reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_SET_MSK) != 0) |
| 245 | return -EPERM; |
| 246 | |
| 247 | if ((reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_OE_SET_MSK) == 0) |
| 248 | return -EPERM; |
| 249 | |
| 250 | return 0; |
| 251 | } |
| 252 | |
| 253 | /* Start the FPGA programming by initialize the FPGA Manager */ |
| 254 | int fpgamgr_program_init(u32 * rbf_data, size_t rbf_size) |
| 255 | { |
| 256 | int ret; |
| 257 | |
| 258 | /* Step 1 */ |
| 259 | if (fpgamgr_verify_msel()) |
| 260 | return -EPERM; |
| 261 | |
| 262 | /* Step 2 */ |
| 263 | if (fpgamgr_set_cdratio_cdwidth(CFGWDTH_32, rbf_data, rbf_size)) |
| 264 | return -EPERM; |
| 265 | |
| 266 | /* |
| 267 | * Step 3: |
| 268 | * Make sure no other external devices are trying to interfere with |
| 269 | * programming: |
| 270 | */ |
| 271 | if (wait_for_nconfig_pin_and_nstatus_pin()) |
| 272 | return -ETIME; |
| 273 | |
| 274 | /* |
| 275 | * Step 4: |
| 276 | * Deassert the signal drives from HPS |
| 277 | * |
| 278 | * S2F_NCE = 1 |
| 279 | * S2F_PR_REQUEST = 0 |
| 280 | * EN_CFG_CTRL = 0 |
| 281 | * EN_CFG_DATA = 0 |
| 282 | * S2F_NCONFIG = 1 |
| 283 | * S2F_NSTATUS_OE = 0 |
| 284 | * S2F_CONDONE_OE = 0 |
| 285 | */ |
| 286 | setbits_le32(&fpga_manager_base->imgcfg_ctrl_01, |
| 287 | ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NCE_SET_MSK); |
| 288 | |
| 289 | clrbits_le32(&fpga_manager_base->imgcfg_ctrl_01, |
| 290 | ALT_FPGAMGR_IMGCFG_CTL_01_S2F_PR_REQUEST_SET_MSK); |
| 291 | |
| 292 | clrbits_le32(&fpga_manager_base->imgcfg_ctrl_02, |
| 293 | ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA_SET_MSK | |
| 294 | ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTRL_SET_MSK); |
| 295 | |
| 296 | setbits_le32(&fpga_manager_base->imgcfg_ctrl_00, |
| 297 | ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NCONFIG_SET_MSK); |
| 298 | |
| 299 | clrbits_le32(&fpga_manager_base->imgcfg_ctrl_00, |
| 300 | ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NSTATUS_OE_SET_MSK | |
| 301 | ALT_FPGAMGR_IMGCFG_CTL_00_S2F_CONDONE_OE_SET_MSK); |
| 302 | |
| 303 | /* |
| 304 | * Step 5: |
| 305 | * Enable overrides |
| 306 | * S2F_NENABLE_CONFIG = 0 |
| 307 | * S2F_NENABLE_NCONFIG = 0 |
| 308 | */ |
| 309 | clrbits_le32(&fpga_manager_base->imgcfg_ctrl_01, |
| 310 | ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NENABLE_CONFIG_SET_MSK); |
| 311 | clrbits_le32(&fpga_manager_base->imgcfg_ctrl_00, |
| 312 | ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NCONFIG_SET_MSK); |
| 313 | |
| 314 | /* |
| 315 | * Disable driving signals that HPS doesn't need to drive. |
| 316 | * S2F_NENABLE_NSTATUS = 1 |
| 317 | * S2F_NENABLE_CONDONE = 1 |
| 318 | */ |
| 319 | setbits_le32(&fpga_manager_base->imgcfg_ctrl_00, |
| 320 | ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NSTATUS_SET_MSK | |
| 321 | ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_CONDONE_SET_MSK); |
| 322 | |
| 323 | /* |
| 324 | * Step 6: |
| 325 | * Drive chip select S2F_NCE = 0 |
| 326 | */ |
| 327 | clrbits_le32(&fpga_manager_base->imgcfg_ctrl_01, |
| 328 | ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NCE_SET_MSK); |
| 329 | |
| 330 | /* Step 7 */ |
| 331 | if (wait_for_nconfig_pin_and_nstatus_pin()) |
| 332 | return -ETIME; |
| 333 | |
| 334 | /* Step 8 */ |
| 335 | ret = fpgamgr_reset(); |
| 336 | |
| 337 | if (ret) |
| 338 | return ret; |
| 339 | |
| 340 | /* |
| 341 | * Step 9: |
| 342 | * EN_CFG_CTRL and EN_CFG_DATA = 1 |
| 343 | */ |
| 344 | setbits_le32(&fpga_manager_base->imgcfg_ctrl_02, |
| 345 | ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA_SET_MSK | |
| 346 | ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTRL_SET_MSK); |
| 347 | |
| 348 | return 0; |
| 349 | } |
| 350 | |
| 351 | /* Ensure the FPGA entering config done */ |
| 352 | static int fpgamgr_program_poll_cd(void) |
| 353 | { |
| 354 | unsigned long reg, i; |
| 355 | |
| 356 | for (i = 0; i < FPGA_TIMEOUT_CNT; i++) { |
| 357 | reg = readl(&fpga_manager_base->imgcfg_stat); |
| 358 | if (reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_SET_MSK) |
| 359 | return 0; |
| 360 | |
| 361 | if ((reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK) == 0) { |
| 362 | printf("nstatus == 0 while waiting for condone\n"); |
| 363 | return -EPERM; |
| 364 | } |
| 365 | } |
| 366 | |
| 367 | if (i == FPGA_TIMEOUT_CNT) |
| 368 | return -ETIME; |
| 369 | |
| 370 | return 0; |
| 371 | } |
| 372 | |
| 373 | /* Ensure the FPGA entering user mode */ |
| 374 | static int fpgamgr_program_poll_usermode(void) |
| 375 | { |
| 376 | unsigned long reg; |
| 377 | int ret = 0; |
| 378 | |
| 379 | if (fpgamgr_dclkcnt_set(0xf)) |
| 380 | return -ETIME; |
| 381 | |
| 382 | ret = wait_for_user_mode(); |
| 383 | if (ret < 0) { |
| 384 | printf("%s: Failed to enter user mode with ", __func__); |
| 385 | printf("error code %d\n", ret); |
| 386 | return ret; |
| 387 | } |
| 388 | |
| 389 | /* |
| 390 | * Step 14: |
| 391 | * Stop DATA path and Dclk |
| 392 | * EN_CFG_CTRL and EN_CFG_DATA = 0 |
| 393 | */ |
| 394 | clrbits_le32(&fpga_manager_base->imgcfg_ctrl_02, |
| 395 | ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA_SET_MSK | |
| 396 | ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTRL_SET_MSK); |
| 397 | |
| 398 | /* |
| 399 | * Step 15: |
| 400 | * Disable overrides |
| 401 | * S2F_NENABLE_CONFIG = 1 |
| 402 | * S2F_NENABLE_NCONFIG = 1 |
| 403 | */ |
| 404 | setbits_le32(&fpga_manager_base->imgcfg_ctrl_01, |
| 405 | ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NENABLE_CONFIG_SET_MSK); |
| 406 | setbits_le32(&fpga_manager_base->imgcfg_ctrl_00, |
| 407 | ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NCONFIG_SET_MSK); |
| 408 | |
| 409 | /* Disable chip select S2F_NCE = 1 */ |
| 410 | setbits_le32(&fpga_manager_base->imgcfg_ctrl_01, |
| 411 | ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NCE_SET_MSK); |
| 412 | |
| 413 | /* |
| 414 | * Step 16: |
| 415 | * Final check |
| 416 | */ |
| 417 | reg = readl(&fpga_manager_base->imgcfg_stat); |
| 418 | if (((reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK) != |
| 419 | ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK) || |
| 420 | ((reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_SET_MSK) != |
| 421 | ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_SET_MSK) || |
| 422 | ((reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK) != |
| 423 | ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK)) |
| 424 | return -EPERM; |
| 425 | |
| 426 | return 0; |
| 427 | } |
| 428 | |
| 429 | int fpgamgr_program_finish(void) |
| 430 | { |
| 431 | /* Ensure the FPGA entering config done */ |
| 432 | int status = fpgamgr_program_poll_cd(); |
| 433 | |
| 434 | if (status) { |
| 435 | printf("FPGA: Poll CD failed with error code %d\n", status); |
| 436 | return -EPERM; |
| 437 | } |
| 438 | WATCHDOG_RESET(); |
| 439 | |
| 440 | /* Ensure the FPGA entering user mode */ |
| 441 | status = fpgamgr_program_poll_usermode(); |
| 442 | if (status) { |
| 443 | printf("FPGA: Poll usermode failed with error code %d\n", |
| 444 | status); |
| 445 | return -EPERM; |
| 446 | } |
| 447 | |
| 448 | printf("Full Configuration Succeeded.\n"); |
| 449 | |
| 450 | return 0; |
| 451 | } |
| 452 | |
| 453 | /* |
| 454 | * FPGA Manager to program the FPGA. This is the interface used by FPGA driver. |
| 455 | * Return 0 for sucess, non-zero for error. |
| 456 | */ |
| 457 | int socfpga_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size) |
| 458 | { |
| 459 | unsigned long status; |
| 460 | |
| 461 | /* disable all signals from hps peripheral controller to fpga */ |
| 462 | writel(0, &system_manager_base->fpgaintf_en_global); |
| 463 | |
| 464 | /* disable all axi bridge (hps2fpga, lwhps2fpga & fpga2hps) */ |
| 465 | socfpga_bridges_reset(); |
| 466 | |
| 467 | /* Initialize the FPGA Manager */ |
| 468 | status = fpgamgr_program_init((u32 *)rbf_data, rbf_size); |
| 469 | if (status) |
| 470 | return status; |
| 471 | |
| 472 | /* Write the RBF data to FPGA Manager */ |
| 473 | fpgamgr_program_write(rbf_data, rbf_size); |
| 474 | |
| 475 | return fpgamgr_program_finish(); |
| 476 | } |