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git01.mediatek.com / filogic / uboot / 2ba0a689e6b3c30f8d6feea31b957bad485e41ec / . / test / dm / panel.c
blob: 7e4ebd6d81e6f6163878f07919cd92873d5b2fa8 [file] [log] [blame]
Simon Glass5620cf82018-10-01 12:22:40 -0600[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Test for panel uclass
4 *
5 * Copyright (c) 2018 Google, Inc
6 * Written by Simon Glass <sjg@chromium.org>
7 */
8
9#include <common.h>
10#include <backlight.h>
11#include <dm.h>
12#include <panel.h>
13#include <video.h>
14#include <asm/gpio.h>
15#include <asm/test.h>
16#include <dm/test.h>
17#include <test/ut.h>
18#include <power/regulator.h>
19
20/* Basic test of the panel uclass */
21static int dm_test_panel(struct unit_test_state *uts)
22{
23 struct udevice *dev, *pwm, *gpio, *reg;
24 uint period_ns;
25 uint duty_ns;
26 bool enable;
27 bool polarity;
28
29 ut_assertok(uclass_first_device_err(UCLASS_PANEL, &dev));
30 ut_assertok(uclass_first_device_err(UCLASS_PWM, &pwm));
31 ut_assertok(uclass_get_device(UCLASS_GPIO, 1, &gpio));
32 ut_assertok(regulator_get_by_platname("VDD_EMMC_1.8V", &reg));
33 ut_assertok(sandbox_pwm_get_config(pwm, 0, &period_ns, &duty_ns,
34 &enable, &polarity));
35 ut_asserteq(false, enable);
36 ut_asserteq(false, regulator_get_enable(reg));
37
38 ut_assertok(panel_enable_backlight(dev));
39 ut_assertok(sandbox_pwm_get_config(pwm, 0, &period_ns, &duty_ns,
40 &enable, &polarity));
41 ut_asserteq(1000, period_ns);
42 ut_asserteq(170 * 1000 / 256, duty_ns);
43 ut_asserteq(true, enable);
44 ut_asserteq(false, polarity);
45 ut_asserteq(1, sandbox_gpio_get_value(gpio, 1));
46 ut_asserteq(true, regulator_get_enable(reg));
47
Simon Glassfe68a452018-10-01 12:22:41 -0600[diff] [blame]48 ut_assertok(panel_set_backlight(dev, 40));
49 ut_assertok(sandbox_pwm_get_config(pwm, 0, &period_ns, &duty_ns,
50 &enable, &polarity));
51 ut_asserteq(64 * 1000 / 256, duty_ns);
52
53 ut_assertok(panel_set_backlight(dev, BACKLIGHT_MAX));
54 ut_assertok(sandbox_pwm_get_config(pwm, 0, &period_ns, &duty_ns,
55 &enable, &polarity));
56 ut_asserteq(255 * 1000 / 256, duty_ns);
57
58 ut_assertok(panel_set_backlight(dev, BACKLIGHT_MIN));
59 ut_assertok(sandbox_pwm_get_config(pwm, 0, &period_ns, &duty_ns,
60 &enable, &polarity));
61 ut_asserteq(0 * 1000 / 256, duty_ns);
62 ut_asserteq(1, sandbox_gpio_get_value(gpio, 1));
63
64 ut_assertok(panel_set_backlight(dev, BACKLIGHT_DEFAULT));
65 ut_assertok(sandbox_pwm_get_config(pwm, 0, &period_ns, &duty_ns,
66 &enable, &polarity));
67 ut_asserteq(true, enable);
68 ut_asserteq(170 * 1000 / 256, duty_ns);
69
70 ut_assertok(panel_set_backlight(dev, BACKLIGHT_OFF));
71 ut_assertok(sandbox_pwm_get_config(pwm, 0, &period_ns, &duty_ns,
72 &enable, &polarity));
73 ut_asserteq(0 * 1000 / 256, duty_ns);
74 ut_asserteq(0, sandbox_gpio_get_value(gpio, 1));
75 ut_asserteq(false, regulator_get_enable(reg));
76
Simon Glass5620cf82018-10-01 12:22:40 -0600[diff] [blame]77 return 0;
78}
79DM_TEST(dm_test_panel, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);