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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0
Ley Foon Tancfd0c542017-04-26 02:44:43 +08002/*
3 * Copyright (C) 2016-2017 Intel Corporation
Ley Foon Tancfd0c542017-04-26 02:44:43 +08004 */
5
6#include <altera.h>
7#include <common.h>
8#include <errno.h>
9#include <fdtdec.h>
10#include <miiphy.h>
11#include <netdev.h>
12#include <ns16550.h>
13#include <watchdog.h>
14#include <asm/arch/misc.h>
15#include <asm/arch/pinmux.h>
16#include <asm/arch/reset_manager.h>
Ley Foon Tan2b963522018-06-01 16:13:19 +080017#include <asm/arch/reset_manager_arria10.h>
Ley Foon Tancfd0c542017-04-26 02:44:43 +080018#include <asm/arch/sdram_arria10.h>
19#include <asm/arch/system_manager.h>
20#include <asm/arch/nic301.h>
21#include <asm/io.h>
22#include <asm/pl310.h>
23
24#define PINMUX_UART0_TX_SHARED_IO_OFFSET_Q1_3 0x08
25#define PINMUX_UART0_TX_SHARED_IO_OFFSET_Q2_11 0x58
26#define PINMUX_UART0_TX_SHARED_IO_OFFSET_Q3_3 0x68
27#define PINMUX_UART1_TX_SHARED_IO_OFFSET_Q1_7 0x18
28#define PINMUX_UART1_TX_SHARED_IO_OFFSET_Q3_7 0x78
29#define PINMUX_UART1_TX_SHARED_IO_OFFSET_Q4_3 0x98
30
Ley Foon Tancfd0c542017-04-26 02:44:43 +080031#if defined(CONFIG_SPL_BUILD)
32static struct pl310_regs *const pl310 =
33 (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
34static const struct socfpga_noc_fw_ocram *noc_fw_ocram_base =
35 (void *)SOCFPGA_SDR_FIREWALL_OCRAM_ADDRESS;
36#endif
37
38static struct socfpga_system_manager *sysmgr_regs =
39 (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
40
41/*
42 * DesignWare Ethernet initialization
43 */
44#ifdef CONFIG_ETH_DESIGNWARE
Marek Vasut3386c852018-04-23 22:49:31 +020045static void arria10_dwmac_reset(const u8 of_reset_id, const u8 phymode)
Ley Foon Tancfd0c542017-04-26 02:44:43 +080046{
47 u32 reset;
48
49 if (of_reset_id == EMAC0_RESET) {
50 reset = SOCFPGA_RESET(EMAC0);
51 } else if (of_reset_id == EMAC1_RESET) {
52 reset = SOCFPGA_RESET(EMAC1);
53 } else if (of_reset_id == EMAC2_RESET) {
54 reset = SOCFPGA_RESET(EMAC2);
55 } else {
56 printf("GMAC: Invalid reset ID (%i)!\n", of_reset_id);
57 return;
58 }
59
60 clrsetbits_le32(&sysmgr_regs->emac[of_reset_id - EMAC0_RESET],
61 SYSMGR_EMACGRP_CTRL_PHYSEL_MASK,
62 phymode);
63
64 /* Release the EMAC controller from reset */
65 socfpga_per_reset(reset, 0);
66}
Marek Vasut3386c852018-04-23 22:49:31 +020067
68static int socfpga_eth_reset(void)
69{
70 /* Put all GMACs into RESET state. */
71 socfpga_per_reset(SOCFPGA_RESET(EMAC0), 1);
72 socfpga_per_reset(SOCFPGA_RESET(EMAC1), 1);
73 socfpga_per_reset(SOCFPGA_RESET(EMAC2), 1);
74 return socfpga_eth_reset_common(arria10_dwmac_reset);
75};
76#else
77static int socfpga_eth_reset(void)
78{
79 return 0;
80};
Ley Foon Tancfd0c542017-04-26 02:44:43 +080081#endif
82
83#if defined(CONFIG_SPL_BUILD)
84/*
85+ * This function initializes security policies to be consistent across
86+ * all logic units in the Arria 10.
87+ *
88+ * The idea is to set all security policies to be normal, nonsecure
89+ * for all units.
90+ */
91static void initialize_security_policies(void)
92{
93 /* Put OCRAM in non-secure */
94 writel(0x003f0000, &noc_fw_ocram_base->region0);
95 writel(0x1, &noc_fw_ocram_base->enable);
96}
97
98int arch_early_init_r(void)
99{
100 initialize_security_policies();
101
102 /* Configure the L2 controller to make SDRAM start at 0 */
103 writel(0x1, &pl310->pl310_addr_filter_start);
104
105 /* assert reset to all except L4WD0 and L4TIMER0 */
106 socfpga_per_reset_all();
107
Ley Foon Tancfd0c542017-04-26 02:44:43 +0800108 return 0;
109}
110#else
111int arch_early_init_r(void)
112{
113 return 0;
114}
115#endif
116
117/*
118 * This function looking the 1st encounter UART peripheral,
119 * and then return its offset of the dedicated/shared IO pin
120 * mux. offset value (zero and above).
121 */
122static int find_peripheral_uart(const void *blob,
123 int child, const char *node_name)
124{
125 int len;
126 fdt_addr_t base_addr = 0;
127 fdt_size_t size;
128 const u32 *cell;
129 u32 value, offset = 0;
130
131 base_addr = fdtdec_get_addr_size(blob, child, "reg", &size);
132 if (base_addr != FDT_ADDR_T_NONE) {
133 cell = fdt_getprop(blob, child, "pinctrl-single,pins",
134 &len);
135 if (cell != NULL) {
136 for (; len > 0; len -= (2 * sizeof(u32))) {
137 offset = fdt32_to_cpu(*cell++);
138 value = fdt32_to_cpu(*cell++);
139 /* Found UART peripheral. */
140 if (value == PINMUX_UART)
141 return offset;
142 }
143 }
144 }
145 return -EINVAL;
146}
147
148/*
149 * This function looks up the 1st encounter UART peripheral,
150 * and then return its offset of the dedicated/shared IO pin
151 * mux. UART peripheral is found if the offset is not in negative
152 * value.
153 */
154static int is_peripheral_uart_true(const void *blob,
155 int node, const char *child_name)
156{
157 int child, len;
158 const char *node_name;
159
160 child = fdt_first_subnode(blob, node);
161
162 if (child < 0)
163 return -EINVAL;
164
165 node_name = fdt_get_name(blob, child, &len);
166
167 while (node_name) {
168 if (!strcmp(child_name, node_name))
169 return find_peripheral_uart(blob, child, node_name);
170
171 child = fdt_next_subnode(blob, child);
172 if (child < 0)
173 break;
174
175 node_name = fdt_get_name(blob, child, &len);
176 }
177
178 return -1;
179}
180
181/*
182 * This function looking the 1st encounter UART dedicated IO peripheral,
183 * and then return based address of the 1st encounter UART dedicated
184 * IO peripheral.
185 */
186unsigned int dedicated_uart_com_port(const void *blob)
187{
188 int node;
189
190 node = fdtdec_next_compatible(blob, 0,
191 COMPAT_ALTERA_SOCFPGA_PINCTRL_SINGLE);
192 if (node < 0)
193 return 0;
194
195 if (is_peripheral_uart_true(blob, node, "dedicated") >= 0)
196 return SOCFPGA_UART1_ADDRESS;
197
198 return 0;
199}
200
201/*
202 * This function looking the 1st encounter UART shared IO peripheral, and then
203 * return based address of the 1st encounter UART shared IO peripheral.
204 */
205unsigned int shared_uart_com_port(const void *blob)
206{
207 int node, ret;
208
209 node = fdtdec_next_compatible(blob, 0,
210 COMPAT_ALTERA_SOCFPGA_PINCTRL_SINGLE);
211 if (node < 0)
212 return 0;
213
214 ret = is_peripheral_uart_true(blob, node, "shared");
215
216 if (ret == PINMUX_UART0_TX_SHARED_IO_OFFSET_Q1_3 ||
217 ret == PINMUX_UART0_TX_SHARED_IO_OFFSET_Q2_11 ||
218 ret == PINMUX_UART0_TX_SHARED_IO_OFFSET_Q3_3)
219 return SOCFPGA_UART0_ADDRESS;
220 else if (ret == PINMUX_UART1_TX_SHARED_IO_OFFSET_Q1_7 ||
221 ret == PINMUX_UART1_TX_SHARED_IO_OFFSET_Q3_7 ||
222 ret == PINMUX_UART1_TX_SHARED_IO_OFFSET_Q4_3)
223 return SOCFPGA_UART1_ADDRESS;
224
225 return 0;
226}
227
228/*
229 * This function looking the 1st encounter UART peripheral, and then return
230 * base address of the 1st encounter UART peripheral.
231 */
232unsigned int uart_com_port(const void *blob)
233{
234 unsigned int ret;
235
236 ret = dedicated_uart_com_port(blob);
237
238 if (ret)
239 return ret;
240
241 return shared_uart_com_port(blob);
242}
243
244/*
245 * Print CPU information
246 */
247#if defined(CONFIG_DISPLAY_CPUINFO)
248int print_cpuinfo(void)
249{
250 const u32 bsel =
251 SYSMGR_GET_BOOTINFO_BSEL(readl(&sysmgr_regs->bootinfo));
252
253 puts("CPU: Altera SoCFPGA Arria 10\n");
254
255 printf("BOOT: %s\n", bsel_str[bsel].name);
256 return 0;
257}
258#endif
259
260#ifdef CONFIG_ARCH_MISC_INIT
261int arch_misc_init(void)
262{
Marek Vasut3386c852018-04-23 22:49:31 +0200263 return socfpga_eth_reset();
Ley Foon Tancfd0c542017-04-26 02:44:43 +0800264}
265#endif
Ley Foon Tan2b963522018-06-01 16:13:19 +0800266
267void do_bridge_reset(int enable)
268{
269 if (enable)
270 socfpga_reset_deassert_bridges_handoff();
271 else
272 socfpga_bridges_reset();
273}