Blame - board/pandora/pandora.h - filogic/uboot

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Dirk Behme	7b84a7b	2009-01-28 21:39:58 +0100	[diff] [blame]	1	/*
				2	* (C) Copyright 2008
				3	* Grazvydas Ignotas <notasas@gmail.com>
				4	*
				5	* See file CREDITS for list of people who contributed to this
				6	* project.
				7	*
				8	* This program is free software; you can redistribute it and/or
				9	* modify it under the terms of the GNU General Public License as
				10	* published by the Free Software Foundation; either version 2 of
				11	* the License, or (at your option) any later version.
				12	*
				13	* This program is distributed in the hope that it will be useful,
				14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
				15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
				16	* GNU General Public License for more details.
				17	*
				18	* You should have received a copy of the GNU General Public License
				19	* along with this program; if not, write to the Free Software
				20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
				21	* MA 02111-1307 USA
				22	*/
				23	#ifndef _PANDORA_H_
				24	#define _PANDORA_H_
				25
				26	const omap3_sysinfo sysinfo = {
Dirk Behme	7b84a7b	2009-01-28 21:39:58 +0100	[diff] [blame]	27	DDR_STACKED,
Dirk Behme	7b84a7b	2009-01-28 21:39:58 +0100	[diff] [blame]	28	"OMAP3 Pandora",
				29	"NAND",
				30	};
				31
				32	/*
				33	* IEN - Input Enable
				34	* IDIS - Input Disable
				35	* PTD - Pull type Down
				36	* PTU - Pull type Up
				37	* DIS - Pull type selection is inactive
				38	* EN - Pull type selection is active
				39	* M0 - Mode 0
				40	* The commented string gives the final mux configuration for that pin
				41	*/
				42	#define MUX_PANDORA() \
				43	/SDRC/\
Olof Johansson	4c391e5	2009-09-28 08:19:30 -0400	[diff] [blame]	44	MUX_VAL(CP(SDRC_D0), (IEN \| PTD \| DIS \| M0)) /SDRC_D0/\
				45	MUX_VAL(CP(SDRC_D1), (IEN \| PTD \| DIS \| M0)) /SDRC_D1/\
				46	MUX_VAL(CP(SDRC_D2), (IEN \| PTD \| DIS \| M0)) /SDRC_D2/\
				47	MUX_VAL(CP(SDRC_D3), (IEN \| PTD \| DIS \| M0)) /SDRC_D3/\
				48	MUX_VAL(CP(SDRC_D4), (IEN \| PTD \| DIS \| M0)) /SDRC_D4/\
				49	MUX_VAL(CP(SDRC_D5), (IEN \| PTD \| DIS \| M0)) /SDRC_D5/\
				50	MUX_VAL(CP(SDRC_D6), (IEN \| PTD \| DIS \| M0)) /SDRC_D6/\
				51	MUX_VAL(CP(SDRC_D7), (IEN \| PTD \| DIS \| M0)) /SDRC_D7/\
				52	MUX_VAL(CP(SDRC_D8), (IEN \| PTD \| DIS \| M0)) /SDRC_D8/\
				53	MUX_VAL(CP(SDRC_D9), (IEN \| PTD \| DIS \| M0)) /SDRC_D9/\
				54	MUX_VAL(CP(SDRC_D10), (IEN \| PTD \| DIS \| M0)) /SDRC_D10/\
				55	MUX_VAL(CP(SDRC_D11), (IEN \| PTD \| DIS \| M0)) /SDRC_D11/\
				56	MUX_VAL(CP(SDRC_D12), (IEN \| PTD \| DIS \| M0)) /SDRC_D12/\
				57	MUX_VAL(CP(SDRC_D13), (IEN \| PTD \| DIS \| M0)) /SDRC_D13/\
				58	MUX_VAL(CP(SDRC_D14), (IEN \| PTD \| DIS \| M0)) /SDRC_D14/\
				59	MUX_VAL(CP(SDRC_D15), (IEN \| PTD \| DIS \| M0)) /SDRC_D15/\
				60	MUX_VAL(CP(SDRC_D16), (IEN \| PTD \| DIS \| M0)) /SDRC_D16/\
				61	MUX_VAL(CP(SDRC_D17), (IEN \| PTD \| DIS \| M0)) /SDRC_D17/\
				62	MUX_VAL(CP(SDRC_D18), (IEN \| PTD \| DIS \| M0)) /SDRC_D18/\
				63	MUX_VAL(CP(SDRC_D19), (IEN \| PTD \| DIS \| M0)) /SDRC_D19/\
				64	MUX_VAL(CP(SDRC_D20), (IEN \| PTD \| DIS \| M0)) /SDRC_D20/\
				65	MUX_VAL(CP(SDRC_D21), (IEN \| PTD \| DIS \| M0)) /SDRC_D21/\
				66	MUX_VAL(CP(SDRC_D22), (IEN \| PTD \| DIS \| M0)) /SDRC_D22/\
				67	MUX_VAL(CP(SDRC_D23), (IEN \| PTD \| DIS \| M0)) /SDRC_D23/\
				68	MUX_VAL(CP(SDRC_D24), (IEN \| PTD \| DIS \| M0)) /SDRC_D24/\
				69	MUX_VAL(CP(SDRC_D25), (IEN \| PTD \| DIS \| M0)) /SDRC_D25/\
				70	MUX_VAL(CP(SDRC_D26), (IEN \| PTD \| DIS \| M0)) /SDRC_D26/\
				71	MUX_VAL(CP(SDRC_D27), (IEN \| PTD \| DIS \| M0)) /SDRC_D27/\
				72	MUX_VAL(CP(SDRC_D28), (IEN \| PTD \| DIS \| M0)) /SDRC_D28/\
				73	MUX_VAL(CP(SDRC_D29), (IEN \| PTD \| DIS \| M0)) /SDRC_D29/\
				74	MUX_VAL(CP(SDRC_D30), (IEN \| PTD \| DIS \| M0)) /SDRC_D30/\
				75	MUX_VAL(CP(SDRC_D31), (IEN \| PTD \| DIS \| M0)) /SDRC_D31/\
				76	MUX_VAL(CP(SDRC_CLK), (IEN \| PTD \| DIS \| M0)) /SDRC_CLK/\
				77	MUX_VAL(CP(SDRC_DQS0), (IEN \| PTD \| DIS \| M0)) /SDRC_DQS0/\
				78	MUX_VAL(CP(SDRC_DQS1), (IEN \| PTD \| DIS \| M0)) /SDRC_DQS1/\
				79	MUX_VAL(CP(SDRC_DQS2), (IEN \| PTD \| DIS \| M0)) /SDRC_DQS2/\
				80	MUX_VAL(CP(SDRC_DQS3), (IEN \| PTD \| DIS \| M0)) /SDRC_DQS3/\
Dirk Behme	7b84a7b	2009-01-28 21:39:58 +0100	[diff] [blame]	81	/GPMC/\
Olof Johansson	4c391e5	2009-09-28 08:19:30 -0400	[diff] [blame]	82	MUX_VAL(CP(GPMC_A1), (IDIS \| PTD \| DIS \| M0)) /GPMC_A1/\
				83	MUX_VAL(CP(GPMC_A2), (IDIS \| PTD \| DIS \| M0)) /GPMC_A2/\
				84	MUX_VAL(CP(GPMC_A3), (IDIS \| PTD \| DIS \| M0)) /GPMC_A3/\
				85	MUX_VAL(CP(GPMC_A4), (IDIS \| PTD \| DIS \| M0)) /GPMC_A4/\
				86	MUX_VAL(CP(GPMC_A5), (IDIS \| PTD \| DIS \| M0)) /GPMC_A5/\
				87	MUX_VAL(CP(GPMC_A6), (IDIS \| PTD \| DIS \| M0)) /GPMC_A6/\
				88	MUX_VAL(CP(GPMC_A7), (IDIS \| PTD \| DIS \| M0)) /GPMC_A7/\
				89	MUX_VAL(CP(GPMC_A8), (IDIS \| PTD \| DIS \| M0)) /GPMC_A8/\
				90	MUX_VAL(CP(GPMC_A9), (IDIS \| PTD \| DIS \| M0)) /GPMC_A9/\
				91	MUX_VAL(CP(GPMC_A10), (IDIS \| PTD \| DIS \| M0)) /GPMC_A10/\
				92	MUX_VAL(CP(GPMC_D0), (IEN \| PTD \| DIS \| M0)) /GPMC_D0/\
				93	MUX_VAL(CP(GPMC_D1), (IEN \| PTD \| DIS \| M0)) /GPMC_D1/\
				94	MUX_VAL(CP(GPMC_D2), (IEN \| PTD \| DIS \| M0)) /GPMC_D2/\
				95	MUX_VAL(CP(GPMC_D3), (IEN \| PTD \| DIS \| M0)) /GPMC_D3/\
				96	MUX_VAL(CP(GPMC_D4), (IEN \| PTD \| DIS \| M0)) /GPMC_D4/\
				97	MUX_VAL(CP(GPMC_D5), (IEN \| PTD \| DIS \| M0)) /GPMC_D5/\
				98	MUX_VAL(CP(GPMC_D6), (IEN \| PTD \| DIS \| M0)) /GPMC_D6/\
				99	MUX_VAL(CP(GPMC_D7), (IEN \| PTD \| DIS \| M0)) /GPMC_D7/\
				100	MUX_VAL(CP(GPMC_D8), (IEN \| PTD \| DIS \| M0)) /GPMC_D8/\
				101	MUX_VAL(CP(GPMC_D9), (IEN \| PTD \| DIS \| M0)) /GPMC_D9/\
				102	MUX_VAL(CP(GPMC_D10), (IEN \| PTD \| DIS \| M0)) /GPMC_D10/\
				103	MUX_VAL(CP(GPMC_D11), (IEN \| PTD \| DIS \| M0)) /GPMC_D11/\
				104	MUX_VAL(CP(GPMC_D12), (IEN \| PTD \| DIS \| M0)) /GPMC_D12/\
				105	MUX_VAL(CP(GPMC_D13), (IEN \| PTD \| DIS \| M0)) /GPMC_D13/\
				106	MUX_VAL(CP(GPMC_D14), (IEN \| PTD \| DIS \| M0)) /GPMC_D14/\
				107	MUX_VAL(CP(GPMC_D15), (IEN \| PTD \| DIS \| M0)) /GPMC_D15/\
				108	MUX_VAL(CP(GPMC_NCS0), (IDIS \| PTU \| EN \| M0)) /GPMC_nCS0/\
				109	MUX_VAL(CP(GPMC_NCS1), (IDIS \| PTU \| EN \| M0)) /GPMC_nCS1/\
				110	MUX_VAL(CP(GPMC_CLK), (IDIS \| PTD \| DIS \| M0)) /GPMC_CLK/\
				111	MUX_VAL(CP(GPMC_NADV_ALE), (IDIS \| PTD \| DIS \| M0)) /GPMC_nADV_ALE/\
				112	MUX_VAL(CP(GPMC_NOE), (IDIS \| PTD \| DIS \| M0)) /GPMC_nOE/\
				113	MUX_VAL(CP(GPMC_NWE), (IDIS \| PTD \| DIS \| M0)) /GPMC_nWE/\
				114	MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS \| PTD \| DIS \| M0)) /GPMC_nBE0_CLE/\
				115	MUX_VAL(CP(GPMC_NWP), (IEN \| PTD \| DIS \| M0)) /GPMC_nWP/\
				116	MUX_VAL(CP(GPMC_WAIT0), (IEN \| PTU \| EN \| M0)) /GPMC_WAIT0/\
				117	MUX_VAL(CP(GPMC_WAIT1), (IEN \| PTU \| EN \| M0)) /GPMC_WAIT1/\
Dirk Behme	7b84a7b	2009-01-28 21:39:58 +0100	[diff] [blame]	118	/DSS/\
Olof Johansson	4c391e5	2009-09-28 08:19:30 -0400	[diff] [blame]	119	MUX_VAL(CP(DSS_PCLK), (IDIS \| PTD \| DIS \| M0)) /DSS_PCLK/\
				120	MUX_VAL(CP(DSS_HSYNC), (IDIS \| PTD \| DIS \| M0)) /DSS_HSYNC/\
				121	MUX_VAL(CP(DSS_VSYNC), (IDIS \| PTD \| DIS \| M0)) /DSS_VSYNC/\
				122	MUX_VAL(CP(DSS_ACBIAS), (IDIS \| PTD \| DIS \| M0)) /DSS_ACBIAS/\
				123	MUX_VAL(CP(DSS_DATA0), (IDIS \| PTD \| DIS \| M0)) /DSS_DATA0/\
				124	MUX_VAL(CP(DSS_DATA1), (IDIS \| PTD \| DIS \| M0)) /DSS_DATA1/\
				125	MUX_VAL(CP(DSS_DATA2), (IDIS \| PTD \| DIS \| M0)) /DSS_DATA2/\
				126	MUX_VAL(CP(DSS_DATA3), (IDIS \| PTD \| DIS \| M0)) /DSS_DATA3/\
				127	MUX_VAL(CP(DSS_DATA4), (IDIS \| PTD \| DIS \| M0)) /DSS_DATA4/\
				128	MUX_VAL(CP(DSS_DATA5), (IDIS \| PTD \| DIS \| M0)) /DSS_DATA5/\
				129	MUX_VAL(CP(DSS_DATA6), (IDIS \| PTD \| DIS \| M0)) /DSS_DATA6/\
				130	MUX_VAL(CP(DSS_DATA7), (IDIS \| PTD \| DIS \| M0)) /DSS_DATA7/\
				131	MUX_VAL(CP(DSS_DATA8), (IDIS \| PTD \| DIS \| M0)) /DSS_DATA8/\
				132	MUX_VAL(CP(DSS_DATA9), (IDIS \| PTD \| DIS \| M0)) /DSS_DATA9/\
				133	MUX_VAL(CP(DSS_DATA10), (IDIS \| PTD \| DIS \| M0)) /DSS_DATA10/\
				134	MUX_VAL(CP(DSS_DATA11), (IDIS \| PTD \| DIS \| M0)) /DSS_DATA11/\
				135	MUX_VAL(CP(DSS_DATA12), (IDIS \| PTD \| DIS \| M0)) /DSS_DATA12/\
				136	MUX_VAL(CP(DSS_DATA13), (IDIS \| PTD \| DIS \| M0)) /DSS_DATA13/\
				137	MUX_VAL(CP(DSS_DATA14), (IDIS \| PTD \| DIS \| M0)) /DSS_DATA14/\
				138	MUX_VAL(CP(DSS_DATA15), (IDIS \| PTD \| DIS \| M0)) /DSS_DATA15/\
				139	MUX_VAL(CP(DSS_DATA16), (IDIS \| PTD \| DIS \| M0)) /DSS_DATA16/\
				140	MUX_VAL(CP(DSS_DATA17), (IDIS \| PTD \| DIS \| M0)) /DSS_DATA17/\
				141	MUX_VAL(CP(DSS_DATA18), (IDIS \| PTD \| DIS \| M0)) /DSS_DATA18/\
				142	MUX_VAL(CP(DSS_DATA19), (IDIS \| PTD \| DIS \| M0)) /DSS_DATA19/\
				143	MUX_VAL(CP(DSS_DATA20), (IDIS \| PTD \| DIS \| M0)) /DSS_DATA20/\
				144	MUX_VAL(CP(DSS_DATA21), (IDIS \| PTD \| DIS \| M0)) /DSS_DATA21/\
				145	MUX_VAL(CP(DSS_DATA22), (IDIS \| PTD \| DIS \| M0)) /DSS_DATA22/\
				146	MUX_VAL(CP(DSS_DATA23), (IDIS \| PTD \| DIS \| M0)) /DSS_DATA23/\
Dirk Behme	7b84a7b	2009-01-28 21:39:58 +0100	[diff] [blame]	147	/GPIO based game buttons/\
Olof Johansson	4c391e5	2009-09-28 08:19:30 -0400	[diff] [blame]	148	MUX_VAL(CP(CAM_XCLKA), (IEN \| PTD \| DIS \| M4)) /GPIO_96 - LEFT/\
				149	MUX_VAL(CP(CAM_PCLK), (IEN \| PTD \| DIS \| M4)) /GPIO_97 - L2/\
				150	MUX_VAL(CP(CAM_FLD), (IEN \| PTD \| DIS \| M4)) /GPIO_98 - RIGHT/\
				151	MUX_VAL(CP(CAM_D0), (IEN \| PTD \| DIS \| M4)) /GPIO_99 - MENU/\
				152	MUX_VAL(CP(CAM_D1), (IEN \| PTD \| DIS \| M4)) /GPIO_100 - START/\
				153	MUX_VAL(CP(CAM_D2), (IEN \| PTD \| DIS \| M4)) /GPIO_101 - Y/\
				154	MUX_VAL(CP(CAM_D3), (IEN \| PTD \| DIS \| M4)) /GPIO_102 - L1/\
				155	MUX_VAL(CP(CAM_D4), (IEN \| PTD \| DIS \| M4)) /GPIO_103 - DOWN/\
				156	MUX_VAL(CP(CAM_D5), (IEN \| PTD \| DIS \| M4)) /GPIO_104 - SELECT/\
				157	MUX_VAL(CP(CAM_D6), (IEN \| PTD \| DIS \| M4)) /GPIO_105 - R1/\
				158	MUX_VAL(CP(CAM_D7), (IEN \| PTD \| DIS \| M4)) /GPIO_106 - B/\
				159	MUX_VAL(CP(CAM_D8), (IEN \| PTD \| DIS \| M4)) /GPIO_107 - R2/\
				160	MUX_VAL(CP(CAM_D10), (IEN \| PTD \| DIS \| M4)) /GPIO_109 - X/\
				161	MUX_VAL(CP(CAM_D11), (IEN \| PTD \| DIS \| M4)) /GPIO_110 - UP/\
				162	MUX_VAL(CP(CAM_XCLKB), (IEN \| PTD \| DIS \| M4)) /GPIO_111 - A/\
Dirk Behme	7b84a7b	2009-01-28 21:39:58 +0100	[diff] [blame]	163	/Audio Interface To External DAC (Headphone, Speakers)/\
Olof Johansson	4c391e5	2009-09-28 08:19:30 -0400	[diff] [blame]	164	MUX_VAL(CP(MCBSP2_FSX), (IDIS \| PTD \| DIS \| M0)) /McBSP2_FSX/\
				165	MUX_VAL(CP(MCBSP2_CLKX), (IDIS \| PTD \| DIS \| M0)) /McBSP2_CLKX/\
				166	MUX_VAL(CP(MCBSP2_DX), (IDIS \| PTD \| DIS \| M0)) /McBSP2_DX/\
				167	MUX_VAL(CP(MCBSP_CLKS), (IEN \| PTD \| DIS \| M0)) /McBSP_CLKS/\
				168	MUX_VAL(CP(MCBSP2_DR), (IDIS \| PTD \| DIS \| M4)) /GPIO_118/\
				169	/* - nPOWERDOWN_DAC*/\
Dirk Behme	7b84a7b	2009-01-28 21:39:58 +0100	[diff] [blame]	170	/Expansion card 1/\
Olof Johansson	4c391e5	2009-09-28 08:19:30 -0400	[diff] [blame]	171	MUX_VAL(CP(MMC1_CLK), (IDIS \| PTU \| EN \| M0)) /MMC1_CLK/\
				172	MUX_VAL(CP(MMC1_CMD), (IEN \| PTU \| EN \| M0)) /MMC1_CMD/\
				173	MUX_VAL(CP(MMC1_DAT0), (IEN \| PTU \| EN \| M0)) /MMC1_DAT0/\
				174	MUX_VAL(CP(MMC1_DAT1), (IEN \| PTU \| EN \| M0)) /MMC1_DAT1/\
				175	MUX_VAL(CP(MMC1_DAT2), (IEN \| PTU \| EN \| M0)) /MMC1_DAT2/\
				176	MUX_VAL(CP(MMC1_DAT3), (IEN \| PTU \| EN \| M0)) /MMC1_DAT3/\
				177	MUX_VAL(CP(MMC1_DAT4), (IEN \| PTD \| DIS \| M4)) /GPIO_126 - MMC1_WP/\
Dirk Behme	7b84a7b	2009-01-28 21:39:58 +0100	[diff] [blame]	178	/Expansion card 2/\
Olof Johansson	4c391e5	2009-09-28 08:19:30 -0400	[diff] [blame]	179	MUX_VAL(CP(MMC2_CLK), (IDIS \| PTD \| DIS \| M0)) /MMC2_CLK/\
				180	MUX_VAL(CP(MMC2_CMD), (IEN \| PTU \| EN \| M0)) /MMC2_CMD/\
				181	MUX_VAL(CP(MMC2_DAT0), (IEN \| PTU \| EN \| M0)) /MMC2_DAT0/\
				182	MUX_VAL(CP(MMC2_DAT1), (IEN \| PTU \| EN \| M0)) /MMC2_DAT1/\
				183	MUX_VAL(CP(MMC2_DAT2), (IEN \| PTU \| EN \| M0)) /MMC2_DAT2/\
				184	MUX_VAL(CP(MMC2_DAT3), (IEN \| PTU \| EN \| M0)) /MMC2_DAT3/\
				185	MUX_VAL(CP(MMC2_DAT4), (IDIS \| PTD \| DIS \| M1)) /MMC2_DIR_DAT0/\
				186	MUX_VAL(CP(MMC2_DAT5), (IDIS \| PTD \| DIS \| M1)) /MMC2_DIR_DAT1/\
				187	MUX_VAL(CP(MMC2_DAT6), (IDIS \| PTD \| DIS \| M1)) /MMC2_DIR_CMD /\
				188	MUX_VAL(CP(MMC2_DAT7), (IEN \| PTU \| EN \| M1)) /MMC2_CLKIN/\
				189	MUX_VAL(CP(MMC1_DAT5), (IEN \| PTD \| DIS \| M4)) /GPIO_127 - MMC2_WP/\
Dirk Behme	7b84a7b	2009-01-28 21:39:58 +0100	[diff] [blame]	190	/SDIO Interface to WIFI Module/\
Olof Johansson	4c391e5	2009-09-28 08:19:30 -0400	[diff] [blame]	191	MUX_VAL(CP(ETK_CLK_ES2), (IEN \| PTD \| DIS \| M2)) /MMC3_CLK/\
				192	MUX_VAL(CP(ETK_CTL_ES2), (IEN \| PTU \| EN \| M2)) /MMC3_CMD/\
				193	MUX_VAL(CP(ETK_D4_ES2), (IEN \| PTU \| EN \| M2)) /MMC3_DAT0/\
				194	MUX_VAL(CP(ETK_D5_ES2), (IEN \| PTU \| EN \| M2)) /MMC3_DAT1/\
				195	MUX_VAL(CP(ETK_D6_ES2), (IEN \| PTU \| EN \| M2)) /MMC3_DAT2/\
				196	MUX_VAL(CP(ETK_D3_ES2), (IEN \| PTU \| EN \| M2)) /MMC3_DAT3/\
Dirk Behme	7b84a7b	2009-01-28 21:39:58 +0100	[diff] [blame]	197	/Audio Interface To Bluetooth chip/\
Olof Johansson	4c391e5	2009-09-28 08:19:30 -0400	[diff] [blame]	198	MUX_VAL(CP(MCBSP3_DX), (IDIS \| PTD \| DIS \| M0)) /McBSP3_DX/\
				199	MUX_VAL(CP(MCBSP3_DR), (IEN \| PTD \| DIS \| M0)) /McBSP3_DR/\
				200	MUX_VAL(CP(MCBSP3_CLKX), (IEN \| PTD \| DIS \| M0)) /McBSP3_CLKX/\
				201	MUX_VAL(CP(MCBSP3_FSX), (IEN \| PTD \| DIS \| M0)) /McBSP3_FSX/\
Dirk Behme	7b84a7b	2009-01-28 21:39:58 +0100	[diff] [blame]	202	/Digital Interface to Bluetooth (UART)/\
Olof Johansson	4c391e5	2009-09-28 08:19:30 -0400	[diff] [blame]	203	MUX_VAL(CP(UART1_TX), (IDIS \| PTD \| DIS \| M0)) /UART1_TX/\
				204	MUX_VAL(CP(UART1_RTS), (IDIS \| PTD \| DIS \| M0)) /UART1_RTS/\
				205	MUX_VAL(CP(UART1_CTS), (IEN \| PTU \| EN \| M0)) /UART1_CTS/\
				206	MUX_VAL(CP(UART1_RX), (IEN \| PTD \| DIS \| M0)) /UART1_RX/\
Dirk Behme	7b84a7b	2009-01-28 21:39:58 +0100	[diff] [blame]	207	/Audio Interface to Triton2 chip (TPS65950)/\
Olof Johansson	4c391e5	2009-09-28 08:19:30 -0400	[diff] [blame]	208	MUX_VAL(CP(MCBSP4_CLKX), (IEN \| PTD \| DIS \| M0)) /McBSP4_CLKX/\
				209	MUX_VAL(CP(MCBSP4_DR), (IEN \| PTD \| DIS \| M0)) /McBSP4_DR/\
				210	MUX_VAL(CP(MCBSP4_DX), (IDIS \| PTD \| DIS \| M0)) /McBSP4_DX/\
				211	MUX_VAL(CP(MCBSP4_FSX), (IEN \| PTD \| DIS \| M0)) /McBSP4_FSX/\
Dirk Behme	7b84a7b	2009-01-28 21:39:58 +0100	[diff] [blame]	212	/GPIO definitions for muxed pins on AV connector/\
Olof Johansson	4c391e5	2009-09-28 08:19:30 -0400	[diff] [blame]	213	MUX_VAL(CP(UART2_CTS), (IEN \| PTD \| EN \| M4)) /GPIO_144,/\
				214	/UART2_CTS/\
				215	MUX_VAL(CP(UART2_RTS), (IEN \| PTD \| EN \| M4)) /GPIO_145,/\
				216	/UART2_RTS/\
				217	MUX_VAL(CP(UART2_TX), (IEN \| PTD \| EN \| M4)) /GPIO_146,/\
				218	/UART2_TX/\
				219	MUX_VAL(CP(UART2_RX), (IEN \| PTD \| EN \| M4)) /GPIO_147,/\
				220	/UART2_RX/\
Dirk Behme	7b84a7b	2009-01-28 21:39:58 +0100	[diff] [blame]	221	/Serial Interface (Peripheral boot, Linux console, on AV connector)/\
Grazvydas Ignotas	dae1f77	2009-11-12 11:46:07 +0200	[diff] [blame]	222	/RX pulled up to avoid noise when nothing is connected to serial port/\
				223	MUX_VAL(CP(UART3_RX_IRRX), (IEN \| PTU \| EN \| M0)) /UART3_RX/\
Olof Johansson	4c391e5	2009-09-28 08:19:30 -0400	[diff] [blame]	224	MUX_VAL(CP(UART3_TX_IRTX), (IDIS \| PTD \| DIS \| M0)) /UART3_TX/\
Dirk Behme	7b84a7b	2009-01-28 21:39:58 +0100	[diff] [blame]	225	/LEDs (Controlled by OMAP)/\
Olof Johansson	4c391e5	2009-09-28 08:19:30 -0400	[diff] [blame]	226	MUX_VAL(CP(MMC1_DAT6), (IDIS \| PTD \| DIS \| M4)) /GPIO_128/\
				227	/* - LED_MMC1*/\
				228	MUX_VAL(CP(MMC1_DAT7), (IDIS \| PTD \| DIS \| M4)) /GPIO_129/\
				229	/* - LED_MMC2*/\
				230	MUX_VAL(CP(MCBSP1_DX), (IDIS \| PTD \| DIS \| M4)) /GPIO_158/\
				231	/* - LED_BT*/\
				232	MUX_VAL(CP(MCBSP1_DR), (IDIS \| PTD \| DIS \| M4)) /GPIO_159/\
				233	/* - LED_WIFI*/\
Dirk Behme	7b84a7b	2009-01-28 21:39:58 +0100	[diff] [blame]	234	/Switches/\
Olof Johansson	4c391e5	2009-09-28 08:19:30 -0400	[diff] [blame]	235	MUX_VAL(CP(MCSPI1_CS2), (IEN \| PTD \| DIS \| M4)) /GPIO_176/\
				236	/* - nHOLD_SWITCH*/\
				237	MUX_VAL(CP(CAM_D9), (IEN \| PTD \| DIS \| M4)) /GPIO_108/\
				238	/* - nLID_SWITCH*/\
Dirk Behme	7b84a7b	2009-01-28 21:39:58 +0100	[diff] [blame]	239	/External IRQs/\
Olof Johansson	4c391e5	2009-09-28 08:19:30 -0400	[diff] [blame]	240	MUX_VAL(CP(CAM_HS), (IEN \| PTD \| DIS \| M4)) /GPIO_94/\
				241	/* - nTOUCH_IRQ*/\
				242	MUX_VAL(CP(ETK_D7_ES2), (IEN \| PTD \| DIS \| M4)) /GPIO_21/\
				243	/* - WIFI_IRQ*/\
				244	MUX_VAL(CP(MCBSP1_FSX), (IEN \| PTD \| DIS \| M4)) /GPIO_161/\
				245	/* - nIRQ_NUB1*/\
				246	MUX_VAL(CP(MCBSP1_CLKX), (IEN \| PTD \| DIS \| M4)) /GPIO_162/\
				247	/* - nIRQ_NUB2*/\
Dirk Behme	7b84a7b	2009-01-28 21:39:58 +0100	[diff] [blame]	248	/Various other stuff/\
Olof Johansson	4c391e5	2009-09-28 08:19:30 -0400	[diff] [blame]	249	MUX_VAL(CP(UART3_CTS_RCTX), (IEN \| PTD \| DIS \| M4)) /GPIO_163/\
				250	/* - nOC_USB5*/\
				251	MUX_VAL(CP(ETK_D8_ES2), (IEN \| PTD \| DIS \| M4)) /GPIO_22/\
				252	/* - MSECURE*/\
				253	MUX_VAL(CP(CSI2_DY1), (IEN \| PTD \| DIS \| M4)) /GPIO_115/\
				254	/* - POP_OVERHEAT*/\
Dirk Behme	7b84a7b	2009-01-28 21:39:58 +0100	[diff] [blame]	255	/External Resets and Enables/\
Olof Johansson	4c391e5	2009-09-28 08:19:30 -0400	[diff] [blame]	256	MUX_VAL(CP(ETK_D0_ES2), (IDIS \| PTD \| DIS \| M4)) /GPIO_14/\
				257	/* - nHDPHN_SHUTDOWN*/\
				258	MUX_VAL(CP(ETK_D1_ES2), (IDIS \| PTD \| DIS \| M4)) /GPIO_15/\
				259	/* - nBT_SHUTDOWN*/\
				260	MUX_VAL(CP(ETK_D9_ES2), (IDIS \| PTD \| DIS \| M4)) /GPIO_23/\
				261	/* - nWIFI_RESET*/\
				262	MUX_VAL(CP(MCBSP1_FSR), (IDIS \| PTU \| DIS \| M4)) /GPIO_157/\
				263	/* - nLCD_RESET*/\
				264	MUX_VAL(CP(MCBSP1_CLKR), (IDIS \| PTD \| DIS \| M4)) /GPIO_156/\
				265	/* - RESET_NUBS*/\
				266	MUX_VAL(CP(UART3_RTS_SD), (IDIS \| PTD \| DIS \| M4)) /GPIO_164/\
				267	/* - EN_USB_5V*/\
Grazvydas Ignotas	79caa80	2009-07-08 00:29:59 +0300	[diff] [blame]	268	/Spare GPIOs/\
Olof Johansson	4c391e5	2009-09-28 08:19:30 -0400	[diff] [blame]	269	MUX_VAL(CP(GPMC_NCS7), (IEN \| PTD \| EN \| M4)) /GPIO_58/\
				270	MUX_VAL(CP(GPMC_WAIT2), (IEN \| PTD \| EN \| M4)) /GPIO_64/\
				271	MUX_VAL(CP(GPMC_WAIT3), (IEN \| PTD \| EN \| M4)) /GPIO_65/\
				272	MUX_VAL(CP(CAM_VS), (IEN \| PTU \| EN \| M4)) /GPIO_95/\
				273	MUX_VAL(CP(CAM_WEN), (IEN \| PTD \| EN \| M4)) /GPIO_167/\
				274	MUX_VAL(CP(HDQ_SIO), (IEN \| PTD \| EN \| M4)) /GPIO_170/\
Dirk Behme	7b84a7b	2009-01-28 21:39:58 +0100	[diff] [blame]	275	/HS USB OTG Port (connects to HSUSB0)/\
Olof Johansson	4c391e5	2009-09-28 08:19:30 -0400	[diff] [blame]	276	MUX_VAL(CP(HSUSB0_CLK), (IEN \| PTD \| DIS \| M0)) /HSUSB0_CLK/\
				277	MUX_VAL(CP(HSUSB0_STP), (IDIS \| PTU \| EN \| M0)) /HSUSB0_STP/\
				278	MUX_VAL(CP(HSUSB0_DIR), (IEN \| PTD \| DIS \| M0)) /HSUSB0_DIR/\
				279	MUX_VAL(CP(HSUSB0_NXT), (IEN \| PTD \| DIS \| M0)) /HSUSB0_NXT/\
				280	MUX_VAL(CP(HSUSB0_DATA0), (IEN \| PTD \| DIS \| M0)) /HSUSB0_DATA0/\
				281	MUX_VAL(CP(HSUSB0_DATA1), (IEN \| PTD \| DIS \| M0)) /HSUSB0_DATA1/\
				282	MUX_VAL(CP(HSUSB0_DATA2), (IEN \| PTD \| DIS \| M0)) /HSUSB0_DATA2/\
				283	MUX_VAL(CP(HSUSB0_DATA3), (IEN \| PTD \| DIS \| M0)) /HSUSB0_DATA3/\
				284	MUX_VAL(CP(HSUSB0_DATA4), (IEN \| PTD \| DIS \| M0)) /HSUSB0_DATA4/\
				285	MUX_VAL(CP(HSUSB0_DATA5), (IEN \| PTD \| DIS \| M0)) /HSUSB0_DATA5/\
				286	MUX_VAL(CP(HSUSB0_DATA6), (IEN \| PTD \| DIS \| M0)) /HSUSB0_DATA6/\
				287	MUX_VAL(CP(HSUSB0_DATA7), (IEN \| PTD \| DIS \| M0)) /HSUSB0_DATA7/\
Dirk Behme	7b84a7b	2009-01-28 21:39:58 +0100	[diff] [blame]	288	/I2C Ports/\
Olof Johansson	4c391e5	2009-09-28 08:19:30 -0400	[diff] [blame]	289	MUX_VAL(CP(I2C1_SCL), (IEN \| PTU \| EN \| M0)) /I2C1_SCL - T2_CTRL/\
				290	MUX_VAL(CP(I2C1_SDA), (IEN \| PTU \| EN \| M0)) /I2C1_SDA - T2_CTRL/\
				291	MUX_VAL(CP(I2C3_SCL), (IEN \| PTU \| EN \| M0)) /I2C3_SCL - NUBS/\
				292	MUX_VAL(CP(I2C3_SDA), (IEN \| PTU \| EN \| M0)) /I2C3_SDA - NUBS/\
				293	MUX_VAL(CP(I2C4_SCL), (IEN \| PTU \| EN \| M0)) /I2C4_SCL - T2_SR/\
				294	MUX_VAL(CP(I2C4_SDA), (IEN \| PTU \| EN \| M0)) /I2C4_SDA - T2_SR/\
Dirk Behme	7b84a7b	2009-01-28 21:39:58 +0100	[diff] [blame]	295	/Serial Interface (Touch, LCD control)/\
Olof Johansson	4c391e5	2009-09-28 08:19:30 -0400	[diff] [blame]	296	MUX_VAL(CP(MCSPI1_CLK), (IEN \| PTD \| DIS \| M0)) /McSPI1_CLK/\
				297	MUX_VAL(CP(MCSPI1_SIMO), (IEN \| PTD \| DIS \| M0)) /McSPI1_SIMO/\
				298	MUX_VAL(CP(MCSPI1_SOMI), (IEN \| PTD \| DIS \| M0)) /McSPI1_SOMI/\
				299	MUX_VAL(CP(MCSPI1_CS0), (IDIS \| PTU \| EN \| M0)) /McSPI1_CS0 - TOUCH/\
				300	MUX_VAL(CP(MCSPI1_CS1), (IDIS \| PTU \| EN \| M0)) /McSPI1_CS1 - LCD/\
Dirk Behme	7b84a7b	2009-01-28 21:39:58 +0100	[diff] [blame]	301	/HS USB HOST Port (connects to HSUSB2)/\
Olof Johansson	4c391e5	2009-09-28 08:19:30 -0400	[diff] [blame]	302	MUX_VAL(CP(ETK_D10_ES2), (IDIS \| PTD \| DIS \| M3)) /USB_HOST_CLK/\
				303	MUX_VAL(CP(ETK_D11_ES2), (IDIS \| PTU \| EN \| M3)) /USB_HOST_STP/\
				304	MUX_VAL(CP(ETK_D12_ES2), (IEN \| PTD \| DIS \| M3)) /USB_HOST_DIR/\
				305	MUX_VAL(CP(ETK_D13_ES2), (IEN \| PTD \| DIS \| M3)) /USB_HOST_NXT/\
				306	MUX_VAL(CP(ETK_D14_ES2), (IEN \| PTD \| DIS \| M3)) /USB_HOST_D0/\
				307	MUX_VAL(CP(ETK_D15_ES2), (IEN \| PTD \| DIS \| M3)) /USB_HOST_D1/\
				308	MUX_VAL(CP(MCSPI1_CS3), (IEN \| PTD \| DIS \| M3)) /USB_HOST_D2/\
				309	MUX_VAL(CP(MCSPI2_CS1), (IEN \| PTD \| DIS \| M3)) /USB_HOST_D3/\
				310	MUX_VAL(CP(MCSPI2_SIMO), (IEN \| PTD \| DIS \| M3)) /USB_HOST_D4/\
				311	MUX_VAL(CP(MCSPI2_SOMI), (IEN \| PTD \| DIS \| M3)) /USB_HOST_D5/\
				312	MUX_VAL(CP(MCSPI2_CS0), (IEN \| PTD \| DIS \| M3)) /USB_HOST_D6/\
				313	MUX_VAL(CP(MCSPI2_CLK), (IEN \| PTD \| DIS \| M3)) /USB_HOST_D7/\
				314	MUX_VAL(CP(ETK_D2_ES2), (IDIS \| PTD \| DIS \| M4)) /GPIO_16/\
				315	/* - nRESET_USB_HOST*/\
Dirk Behme	7b84a7b	2009-01-28 21:39:58 +0100	[diff] [blame]	316	/Control and debug /\
Olof Johansson	4c391e5	2009-09-28 08:19:30 -0400	[diff] [blame]	317	MUX_VAL(CP(SYS_32K), (IEN \| PTD \| DIS \| M0)) /SYS_32K/\
				318	MUX_VAL(CP(SYS_CLKREQ), (IEN \| PTD \| DIS \| M0)) /SYS_CLKREQ/\
				319	MUX_VAL(CP(SYS_NIRQ), (IEN \| PTU \| EN \| M0)) /SYS_nIRQ/\
				320	MUX_VAL(CP(SYS_BOOT0), (IEN \| PTD \| DIS \| M4)) /GPIO_2/\
				321	MUX_VAL(CP(SYS_BOOT1), (IEN \| PTD \| DIS \| M4)) /GPIO_3/\
				322	MUX_VAL(CP(SYS_BOOT2), (IEN \| PTD \| DIS \| M4)) /GPIO_4/\
				323	MUX_VAL(CP(SYS_BOOT3), (IEN \| PTD \| DIS \| M4)) /GPIO_5/\
				324	MUX_VAL(CP(SYS_BOOT4), (IEN \| PTD \| DIS \| M4)) /GPIO_6/\
				325	MUX_VAL(CP(SYS_BOOT5), (IEN \| PTD \| DIS \| M4)) /GPIO_7/\
				326	MUX_VAL(CP(SYS_BOOT6), (IEN \| PTD \| DIS \| M4)) /GPIO_8/\
				327	MUX_VAL(CP(SYS_OFF_MODE), (IEN \| PTD \| DIS \| M0)) /SYS_OFF_MODE/\
Dirk Behme	7b84a7b	2009-01-28 21:39:58 +0100	[diff] [blame]	328	/JTAG/\
Olof Johansson	4c391e5	2009-09-28 08:19:30 -0400	[diff] [blame]	329	MUX_VAL(CP(JTAG_nTRST), (IEN \| PTD \| DIS \| M0)) /JTAG_nTRST/\
				330	MUX_VAL(CP(JTAG_TCK), (IEN \| PTD \| DIS \| M0)) /JTAG_TCK/\
				331	MUX_VAL(CP(JTAG_TMS), (IEN \| PTD \| DIS \| M0)) /JTAG_TMS/\
				332	MUX_VAL(CP(JTAG_TDI), (IEN \| PTD \| DIS \| M0)) /JTAG_TDI/\
				333	MUX_VAL(CP(JTAG_EMU0), (IEN \| PTD \| DIS \| M0)) /JTAG_EMU0/\
				334	MUX_VAL(CP(JTAG_EMU1), (IEN \| PTD \| DIS \| M0)) /JTAG_EMU1/\
Dirk Behme	7b84a7b	2009-01-28 21:39:58 +0100	[diff] [blame]	335	/Die to Die stuff/\
Olof Johansson	4c391e5	2009-09-28 08:19:30 -0400	[diff] [blame]	336	MUX_VAL(CP(D2D_MCAD1), (IEN \| PTD \| EN \| M0)) /d2d_mcad1/\
				337	MUX_VAL(CP(D2D_MCAD2), (IEN \| PTD \| EN \| M0)) /d2d_mcad2/\
				338	MUX_VAL(CP(D2D_MCAD3), (IEN \| PTD \| EN \| M0)) /d2d_mcad3/\
				339	MUX_VAL(CP(D2D_MCAD4), (IEN \| PTD \| EN \| M0)) /d2d_mcad4/\
				340	MUX_VAL(CP(D2D_MCAD5), (IEN \| PTD \| EN \| M0)) /d2d_mcad5/\
				341	MUX_VAL(CP(D2D_MCAD6), (IEN \| PTD \| EN \| M0)) /d2d_mcad6/\
				342	MUX_VAL(CP(D2D_MCAD7), (IEN \| PTD \| EN \| M0)) /d2d_mcad7/\
				343	MUX_VAL(CP(D2D_MCAD8), (IEN \| PTD \| EN \| M0)) /d2d_mcad8/\
				344	MUX_VAL(CP(D2D_MCAD9), (IEN \| PTD \| EN \| M0)) /d2d_mcad9/\
				345	MUX_VAL(CP(D2D_MCAD10), (IEN \| PTD \| EN \| M0)) /d2d_mcad10/\
				346	MUX_VAL(CP(D2D_MCAD11), (IEN \| PTD \| EN \| M0)) /d2d_mcad11/\
				347	MUX_VAL(CP(D2D_MCAD12), (IEN \| PTD \| EN \| M0)) /d2d_mcad12/\
				348	MUX_VAL(CP(D2D_MCAD13), (IEN \| PTD \| EN \| M0)) /d2d_mcad13/\
				349	MUX_VAL(CP(D2D_MCAD14), (IEN \| PTD \| EN \| M0)) /d2d_mcad14/\
				350	MUX_VAL(CP(D2D_MCAD15), (IEN \| PTD \| EN \| M0)) /d2d_mcad15/\
				351	MUX_VAL(CP(D2D_MCAD16), (IEN \| PTD \| EN \| M0)) /d2d_mcad16/\
				352	MUX_VAL(CP(D2D_MCAD17), (IEN \| PTD \| EN \| M0)) /d2d_mcad17/\
				353	MUX_VAL(CP(D2D_MCAD18), (IEN \| PTD \| EN \| M0)) /d2d_mcad18/\
				354	MUX_VAL(CP(D2D_MCAD19), (IEN \| PTD \| EN \| M0)) /d2d_mcad19/\
				355	MUX_VAL(CP(D2D_MCAD20), (IEN \| PTD \| EN \| M0)) /d2d_mcad20/\
				356	MUX_VAL(CP(D2D_MCAD21), (IEN \| PTD \| EN \| M0)) /d2d_mcad21/\
				357	MUX_VAL(CP(D2D_MCAD22), (IEN \| PTD \| EN \| M0)) /d2d_mcad22/\
				358	MUX_VAL(CP(D2D_MCAD23), (IEN \| PTD \| EN \| M0)) /d2d_mcad23/\
				359	MUX_VAL(CP(D2D_MCAD24), (IEN \| PTD \| EN \| M0)) /d2d_mcad24/\
				360	MUX_VAL(CP(D2D_MCAD25), (IEN \| PTD \| EN \| M0)) /d2d_mcad25/\
				361	MUX_VAL(CP(D2D_MCAD26), (IEN \| PTD \| EN \| M0)) /d2d_mcad26/\
				362	MUX_VAL(CP(D2D_MCAD27), (IEN \| PTD \| EN \| M0)) /d2d_mcad27/\
				363	MUX_VAL(CP(D2D_MCAD28), (IEN \| PTD \| EN \| M0)) /d2d_mcad28/\
				364	MUX_VAL(CP(D2D_MCAD29), (IEN \| PTD \| EN \| M0)) /d2d_mcad29/\
				365	MUX_VAL(CP(D2D_MCAD30), (IEN \| PTD \| EN \| M0)) /d2d_mcad30/\
				366	MUX_VAL(CP(D2D_MCAD31), (IEN \| PTD \| EN \| M0)) /d2d_mcad31/\
				367	MUX_VAL(CP(D2D_MCAD32), (IEN \| PTD \| EN \| M0)) /d2d_mcad32/\
				368	MUX_VAL(CP(D2D_MCAD33), (IEN \| PTD \| EN \| M0)) /d2d_mcad33/\
				369	MUX_VAL(CP(D2D_MCAD34), (IEN \| PTD \| EN \| M0)) /d2d_mcad34/\
				370	MUX_VAL(CP(D2D_MCAD35), (IEN \| PTD \| EN \| M0)) /d2d_mcad35/\
				371	MUX_VAL(CP(D2D_MCAD36), (IEN \| PTD \| EN \| M0)) /d2d_mcad36/\
				372	MUX_VAL(CP(D2D_CLK26MI), (IEN \| PTD \| DIS \| M0)) /d2d_clk26mi/\
				373	MUX_VAL(CP(D2D_NRESPWRON), (IEN \| PTD \| EN \| M0)) /d2d_nrespwron/\
				374	MUX_VAL(CP(D2D_NRESWARM), (IEN \| PTU \| EN \| M0)) /d2d_nreswarm/\
				375	MUX_VAL(CP(D2D_ARM9NIRQ), (IEN \| PTD \| DIS \| M0)) /d2d_arm9nirq/\
				376	MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN \| PTD \| DIS \| M0)) /d2d_uma2p6fiq/\
				377	MUX_VAL(CP(D2D_SPINT), (IEN \| PTD \| EN \| M0)) /d2d_spint/\
				378	MUX_VAL(CP(D2D_FRINT), (IEN \| PTD \| EN \| M0)) /d2d_frint/\
				379	MUX_VAL(CP(D2D_DMAREQ0), (IEN \| PTD \| DIS \| M0)) /d2d_dmareq0/\
				380	MUX_VAL(CP(D2D_DMAREQ1), (IEN \| PTD \| DIS \| M0)) /d2d_dmareq1/\
				381	MUX_VAL(CP(D2D_DMAREQ2), (IEN \| PTD \| DIS \| M0)) /d2d_dmareq2/\
				382	MUX_VAL(CP(D2D_DMAREQ3), (IEN \| PTD \| DIS \| M0)) /d2d_dmareq3/\
				383	MUX_VAL(CP(D2D_N3GTRST), (IEN \| PTD \| DIS \| M0)) /d2d_n3gtrst/\
				384	MUX_VAL(CP(D2D_N3GTDI), (IEN \| PTD \| DIS \| M0)) /d2d_n3gtdi/\
				385	MUX_VAL(CP(D2D_N3GTDO), (IEN \| PTD \| DIS \| M0)) /d2d_n3gtdo/\
				386	MUX_VAL(CP(D2D_N3GTMS), (IEN \| PTD \| DIS \| M0)) /d2d_n3gtms/\
				387	MUX_VAL(CP(D2D_N3GTCK), (IEN \| PTD \| DIS \| M0)) /d2d_n3gtck/\
				388	MUX_VAL(CP(D2D_N3GRTCK), (IEN \| PTD \| DIS \| M0)) /d2d_n3grtck/\
				389	MUX_VAL(CP(D2D_MSTDBY), (IEN \| PTU \| EN \| M0)) /d2d_mstdby/\
				390	MUX_VAL(CP(D2D_SWAKEUP), (IEN \| PTD \| EN \| M0)) /d2d_swakeup/\
				391	MUX_VAL(CP(D2D_IDLEREQ), (IEN \| PTD \| DIS \| M0)) /d2d_idlereq/\
				392	MUX_VAL(CP(D2D_IDLEACK), (IEN \| PTU \| EN \| M0)) /d2d_idleack/\
				393	MUX_VAL(CP(D2D_MWRITE), (IEN \| PTD \| DIS \| M0)) /d2d_mwrite/\
				394	MUX_VAL(CP(D2D_SWRITE), (IEN \| PTD \| DIS \| M0)) /d2d_swrite/\
				395	MUX_VAL(CP(D2D_MREAD), (IEN \| PTD \| DIS \| M0)) /d2d_mread/\
				396	MUX_VAL(CP(D2D_SREAD), (IEN \| PTD \| DIS \| M0)) /d2d_sread/\
				397	MUX_VAL(CP(D2D_MBUSFLAG), (IEN \| PTD \| DIS \| M0)) /d2d_mbusflag/\
				398	MUX_VAL(CP(D2D_SBUSFLAG), (IEN \| PTD \| DIS \| M0)) /d2d_sbusflag/\
				399	MUX_VAL(CP(SDRC_CKE0), (IDIS \| PTU \| EN \| M0)) /sdrc_cke0/\
				400	MUX_VAL(CP(SDRC_CKE1), (IDIS \| PTU \| EN \| M0)) /sdrc_cke1/
Dirk Behme	7b84a7b	2009-01-28 21:39:58 +0100	[diff] [blame]	401
				402	#endif