blob: 0228b4b30e5ba95ce834360f79a638485b500161 [file] [log] [blame]
Ezequiel Garcia00eb01a2018-01-12 12:33:50 -03001// SPDX-License-Identifier: GPL-2.0
2/*
3 * Bitmain Antminer S9 board DTS
4 *
5 * Copyright (C) 2018 Michal Simek
6 * Copyright (C) 2018 VanguardiaSur
7 */
8/dts-v1/;
9#include "zynq-7000.dtsi"
10
11/ {
12 model = "Bitmain Antminer S9 Board";
13 compatible = "bitmain,antminer-s9", "xlnx,zynq-7000";
14
15 aliases {
16 ethernet0 = &gem0;
17 serial0 = &uart1;
18 mmc0 = &sdhci0;
19 gpio0 = &gpio0;
20 };
21
22 memory@0 {
23 device_type = "memory";
24 reg = <0x0 0x40000000>;
25 };
26
27 reserved-memory {
28 #address-cells = <1>;
29 #size-cells = <1>;
30 ranges;
31
32 bootcount@efffff0 {
33 reg = <0xefffff0 0x10>;
34 no-map;
35 };
36
37 fpga_space@f000000 {
38 reg = <0xf000000 0x1000000>;
39 no-map;
40 };
41 };
42
43 chosen {
44 bootargs = "earlycon";
45 stdout-path = "serial0:115200n8";
46 };
47};
48
49&clkc {
50 ps-clk-frequency = <33333333>;
51};
52
Michael Walle42abea62022-02-23 15:10:34 +010053&nfc0 {
Michal Simek1ad97712021-03-18 16:04:44 +010054 status = "okay";
Michal Simekd9974452023-09-22 12:35:42 +020055 nand@0 {
56 reg = <0>;
57 };
Michal Simek1ad97712021-03-18 16:04:44 +010058};
59
60&smcc {
61 status = "okay";
62};
63
Ezequiel Garcia00eb01a2018-01-12 12:33:50 -030064&gem0 {
65 status = "okay";
66 phy-mode = "rgmii-id";
67 phy-handle = <&ethernet_phy>;
68
69 /* 0362/5e62 */
70 ethernet_phy: ethernet-phy@1 {
71 reg = <1>;
72 };
73};
74
75&sdhci0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -070076 bootph-all;
Ezequiel Garcia00eb01a2018-01-12 12:33:50 -030077 status = "okay";
78 disable-wp;
79};
80
81&uart1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -070082 bootph-all;
Ezequiel Garcia00eb01a2018-01-12 12:33:50 -030083 status = "okay";
84};
85
86&watchdog0 {
87 reset-on-timeout;
88 timeout-sec = <200>;
89};