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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Kim Phillips1cb07e62008-01-16 00:38:05 -06002/*
3 * Copyright (C) 2007 Freescale Semiconductor, Inc.
4 * Kevin Lam <kevin.lam@freescale.com>
5 * Joe D'Abbraccio <joe.d'abbraccio@freescale.com>
Kim Phillips1cb07e62008-01-16 00:38:05 -06006 */
7
8#include <common.h>
Simon Glassdb229612019-08-01 09:46:42 -06009#include <env.h>
Anton Vorontsov3628a932009-06-10 00:25:30 +040010#include <hwconfig.h>
Kim Phillips1cb07e62008-01-16 00:38:05 -060011#include <i2c.h>
Simon Glass0ffd9db2019-12-28 10:45:06 -070012#include <init.h>
Simon Glass4dcacfc2020-05-10 11:40:13 -060013#include <asm/bitops.h>
Simon Glass3ba929a2020-10-30 21:38:53 -060014#include <asm/global_data.h>
Kim Phillips1cb07e62008-01-16 00:38:05 -060015#include <asm/io.h>
Kumar Galab7c3ccf2010-04-20 10:02:24 -050016#include <asm/fsl_mpc83xx_serdes.h>
Jean-Christophe PLAGNIOL-VILLARD5fc8a4b2008-04-02 13:41:21 +020017#include <fdt_support.h>
Kim Phillips1cb07e62008-01-16 00:38:05 -060018#include <spd_sdram.h>
Timur Tabi3e1d49a2008-02-08 13:15:55 -060019#include <vsc7385.h>
Anton Vorontsov3628a932009-06-10 00:25:30 +040020#include <fsl_esdhc.h>
Simon Glassdbd79542020-05-10 11:40:11 -060021#include <linux/delay.h>
Timur Tabi3e1d49a2008-02-08 13:15:55 -060022
Simon Glass39f90ba2017-03-31 08:40:25 -060023DECLARE_GLOBAL_DATA_PTR;
24
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020025#if defined(CONFIG_SYS_DRAM_TEST)
Kim Phillips1cb07e62008-01-16 00:38:05 -060026int
27testdram(void)
28{
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020029 uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
30 uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
Kim Phillips1cb07e62008-01-16 00:38:05 -060031 uint *p;
32
33 printf("Testing DRAM from 0x%08x to 0x%08x\n",
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020034 CONFIG_SYS_MEMTEST_START,
35 CONFIG_SYS_MEMTEST_END);
Kim Phillips1cb07e62008-01-16 00:38:05 -060036
37 printf("DRAM test phase 1:\n");
38 for (p = pstart; p < pend; p++)
39 *p = 0xaaaaaaaa;
40
41 for (p = pstart; p < pend; p++) {
42 if (*p != 0xaaaaaaaa) {
43 printf("DRAM test fails at: %08x\n", (uint) p);
44 return 1;
45 }
46 }
47
48 printf("DRAM test phase 2:\n");
49 for (p = pstart; p < pend; p++)
50 *p = 0x55555555;
51
52 for (p = pstart; p < pend; p++) {
53 if (*p != 0x55555555) {
54 printf("DRAM test fails at: %08x\n", (uint) p);
55 return 1;
56 }
57 }
58
59 printf("DRAM test passed.\n");
60 return 0;
61}
62#endif
63
Peter Tysercb4731f2009-06-30 17:15:50 -050064#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
Kim Phillips1cb07e62008-01-16 00:38:05 -060065void ddr_enable_ecc(unsigned int dram_size);
66#endif
67int fixed_sdram(void);
68
Simon Glassd35f3382017-04-06 12:47:05 -060069int dram_init(void)
Kim Phillips1cb07e62008-01-16 00:38:05 -060070{
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020071 immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
Kim Phillips1cb07e62008-01-16 00:38:05 -060072 u32 msize = 0;
73
74 if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
Simon Glass39f90ba2017-03-31 08:40:25 -060075 return -ENXIO;
Kim Phillips1cb07e62008-01-16 00:38:05 -060076
77#if defined(CONFIG_SPD_EEPROM)
78 msize = spd_sdram();
79#else
80 msize = fixed_sdram();
81#endif
82
Peter Tysercb4731f2009-06-30 17:15:50 -050083#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
Kim Phillips1cb07e62008-01-16 00:38:05 -060084 /* Initialize DDR ECC byte */
85 ddr_enable_ecc(msize * 1024 * 1024);
86#endif
87 /* return total bus DDR size(bytes) */
Simon Glass39f90ba2017-03-31 08:40:25 -060088 gd->ram_size = msize * 1024 * 1024;
89
90 return 0;
Kim Phillips1cb07e62008-01-16 00:38:05 -060091}
92
93#if !defined(CONFIG_SPD_EEPROM)
94/*************************************************************************
95 * fixed sdram init -- doesn't use serial presence detect.
96 ************************************************************************/
97int fixed_sdram(void)
98{
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020099 immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
100 u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
Kim Phillips1cb07e62008-01-16 00:38:05 -0600101 u32 msize_log2 = __ilog2(msize);
102
Mario Six805cac12019-01-21 09:18:16 +0100103 im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000;
Kim Phillips1cb07e62008-01-16 00:38:05 -0600104 im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);
105
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200106 im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE;
Kim Phillips1cb07e62008-01-16 00:38:05 -0600107 udelay(50000);
108
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200109 im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL;
Kim Phillips1cb07e62008-01-16 00:38:05 -0600110 udelay(1000);
111
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200112 im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS;
113 im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
Kim Phillips1cb07e62008-01-16 00:38:05 -0600114 udelay(1000);
115
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200116 im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
117 im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
118 im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
119 im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
120 im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
121 im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
122 im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
123 im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
124 im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
Kim Phillips1cb07e62008-01-16 00:38:05 -0600125 sync();
126 udelay(1000);
127
128 im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
129 udelay(2000);
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200130 return CONFIG_SYS_DDR_SIZE;
Kim Phillips1cb07e62008-01-16 00:38:05 -0600131}
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200132#endif /*!CONFIG_SYS_SPD_EEPROM */
Kim Phillips1cb07e62008-01-16 00:38:05 -0600133
134int checkboard(void)
135{
136 puts("Board: Freescale MPC837xERDB\n");
137 return 0;
138}
139
Anton Vorontsov2b3c0042008-03-24 17:40:43 +0300140int board_early_init_f(void)
141{
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200142 immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
Sinan Akmand068b6a2020-04-04 01:16:47 -0400143#ifdef CONFIG_FSL_SERDES
Anton Vorontsov2b3c0042008-03-24 17:40:43 +0300144 u32 spridr = in_be32(&immr->sysconf.spridr);
145
146 /* we check only part num, and don't look for CPU revisions */
Kim Phillipsecb2d6f2008-03-28 10:19:07 -0500147 switch (PARTID_NO_E(spridr)) {
148 case SPR_8377:
Anton Vorontsov2b3c0042008-03-24 17:40:43 +0300149 fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA,
150 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
Kim Phillipsecb2d6f2008-03-28 10:19:07 -0500151 fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX,
Anton Vorontsov2b3c0042008-03-24 17:40:43 +0300152 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
153 break;
Kim Phillipsecb2d6f2008-03-28 10:19:07 -0500154 case SPR_8378:
Anton Vorontsov642016b2008-10-02 18:31:53 +0400155 fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX,
Anton Vorontsov2b3c0042008-03-24 17:40:43 +0300156 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
157 break;
Kim Phillipsecb2d6f2008-03-28 10:19:07 -0500158 case SPR_8379:
Anton Vorontsov2b3c0042008-03-24 17:40:43 +0300159 fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA,
160 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
Kim Phillipsecb2d6f2008-03-28 10:19:07 -0500161 fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_SATA,
Anton Vorontsov2b3c0042008-03-24 17:40:43 +0300162 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
163 break;
164 default:
165 printf("serdes not configured: unknown CPU part number: "
166 "%04x\n", spridr >> 16);
167 break;
168 }
169#endif /* CONFIG_FSL_SERDES */
Sinan Akmand068b6a2020-04-04 01:16:47 -0400170
171#ifdef CONFIG_FSL_ESDHC
172 clrsetbits_be32(&immr->sysconf.sicrl, SICRL_USB_B, SICRL_USB_B_SD);
173 clrsetbits_be32(&immr->sysconf.sicrh, SICRH_SPI, SICRH_SPI_SD);
174#endif
Anton Vorontsov2b3c0042008-03-24 17:40:43 +0300175 return 0;
176}
177
Anton Vorontsov3628a932009-06-10 00:25:30 +0400178#ifdef CONFIG_FSL_ESDHC
Sinan Akmand068b6a2020-04-04 01:16:47 -0400179#if !(CONFIG_IS_ENABLED(DM_MMC))
Masahiro Yamadaf7ed78b2020-06-26 15:13:33 +0900180int board_mmc_init(struct bd_info *bd)
Anton Vorontsov3628a932009-06-10 00:25:30 +0400181{
182 struct immap __iomem *im = (struct immap __iomem *)CONFIG_SYS_IMMR;
Sinan Akman8dc24e02015-01-20 20:47:01 -0500183 char buffer[HWCONFIG_BUFFER_SIZE] = {0};
184 int esdhc_hwconfig_enabled = 0;
185
Simon Glass64b723f2017-08-03 12:22:12 -0600186 if (env_get_f("hwconfig", buffer, sizeof(buffer)) > 0)
Sinan Akman8dc24e02015-01-20 20:47:01 -0500187 esdhc_hwconfig_enabled = hwconfig_f("esdhc", buffer);
Anton Vorontsov3628a932009-06-10 00:25:30 +0400188
Sinan Akman8dc24e02015-01-20 20:47:01 -0500189 if (esdhc_hwconfig_enabled == 0)
Anton Vorontsov3628a932009-06-10 00:25:30 +0400190 return 0;
191
192 clrsetbits_be32(&im->sysconf.sicrl, SICRL_USB_B, SICRL_USB_B_SD);
193 clrsetbits_be32(&im->sysconf.sicrh, SICRH_SPI, SICRH_SPI_SD);
194
195 return fsl_esdhc_mmc_init(bd);
196}
197#endif
Sinan Akmand068b6a2020-04-04 01:16:47 -0400198#endif
Anton Vorontsov3628a932009-06-10 00:25:30 +0400199
Timur Tabi3e1d49a2008-02-08 13:15:55 -0600200/*
201 * Miscellaneous late-boot configurations
202 *
203 * If a VSC7385 microcode image is present, then upload it.
204*/
205int misc_init_r(void)
206{
207 int rc = 0;
208
209#ifdef CONFIG_VSC7385_IMAGE
210 if (vsc7385_upload_firmware((void *) CONFIG_VSC7385_IMAGE,
211 CONFIG_VSC7385_IMAGE_SIZE)) {
212 puts("Failure uploading VSC7385 microcode.\n");
213 rc = 1;
214 }
215#endif
216
217 return rc;
218}
219
Kim Phillips1cb07e62008-01-16 00:38:05 -0600220#if defined(CONFIG_OF_BOARD_SETUP)
221
Masahiro Yamadaf7ed78b2020-06-26 15:13:33 +0900222int ft_board_setup(void *blob, struct bd_info *bd)
Kim Phillips1cb07e62008-01-16 00:38:05 -0600223{
224#ifdef CONFIG_PCI
225 ft_pci_setup(blob, bd);
226#endif
227 ft_cpu_setup(blob, bd);
Sriram Dash9fd465c2016-09-16 17:12:15 +0530228 fsl_fdt_fixup_dr_usb(blob, bd);
Anton Vorontsov3628a932009-06-10 00:25:30 +0400229 fdt_fixup_esdhc(blob, bd);
Simon Glass2aec3cc2014-10-23 18:58:47 -0600230
231 return 0;
Kim Phillips1cb07e62008-01-16 00:38:05 -0600232}
233#endif /* CONFIG_OF_BOARD_SETUP */