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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Marek Vasut05204f62015-12-05 21:07:23 +01002/*
3 * Altera SoCFPGA common board code
4 *
5 * Copyright (C) 2015 Marek Vasut <marex@denx.de>
Marek Vasut05204f62015-12-05 21:07:23 +01006 */
7
8#include <common.h>
9#include <errno.h>
Tien Fong Cheea5bfce32017-12-05 15:58:07 +080010#include <fdtdec.h>
Simon Glass97589732020-05-10 11:40:02 -060011#include <init.h>
Marek Vasut05204f62015-12-05 21:07:23 +010012#include <asm/arch/reset_manager.h>
Tien Fong Cheea5bfce32017-12-05 15:58:07 +080013#include <asm/arch/clock_manager.h>
Tien Fong Cheef3f525c2017-12-05 15:58:08 +080014#include <asm/arch/misc.h>
Simon Glass3ba929a2020-10-30 21:38:53 -060015#include <asm/global_data.h>
Marek Vasut05204f62015-12-05 21:07:23 +010016#include <asm/io.h>
Chee Hong Ang7cfcc0c2020-12-24 18:20:56 +080017#include <log.h>
Marek Vasut05204f62015-12-05 21:07:23 +010018#include <usb.h>
19#include <usb/dwc2_udc.h>
20
21DECLARE_GLOBAL_DATA_PTR;
22
Marek Vasut72cc9582018-05-29 16:16:46 +020023void s_init(void) {
Ley Foon Tan27f05ac2018-07-12 19:13:34 +080024#ifndef CONFIG_ARM64
Marek Vasut72cc9582018-05-29 16:16:46 +020025 /*
Marek Vasut911a6652018-07-12 15:07:46 +020026 * Preconfigure ACTLR and CPACR, make sure Write Full Line of Zeroes
27 * is disabled in ACTLR.
Marek Vasut72cc9582018-05-29 16:16:46 +020028 * This is optional on CycloneV / ArriaV.
29 * This is mandatory on Arria10, otherwise Linux refuses to boot.
30 */
31 asm volatile(
32 "mcr p15, 0, %0, c1, c0, 1\n"
Marek Vasut911a6652018-07-12 15:07:46 +020033 "mcr p15, 0, %0, c1, c0, 2\n"
Marek Vasut72cc9582018-05-29 16:16:46 +020034 "isb\n"
35 "dsb\n"
36 ::"r"(0x0));
Ley Foon Tan27f05ac2018-07-12 19:13:34 +080037#endif
Marek Vasut72cc9582018-05-29 16:16:46 +020038}
Marek Vasut05204f62015-12-05 21:07:23 +010039
40/*
41 * Miscellaneous platform dependent initialisations
42 */
43int board_init(void)
44{
45 /* Address of boot parameters for ATAG (if ATAG is used) */
46 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
47
48 return 0;
49}
50
Tien Fong Chee3710de72017-12-05 15:58:01 +080051int dram_init_banksize(void)
52{
53 fdtdec_setup_memory_banksize();
54
55 return 0;
56}
57
Marek Vasut05204f62015-12-05 21:07:23 +010058#ifdef CONFIG_USB_GADGET
59struct dwc2_plat_otg_data socfpga_otg_data = {
60 .usb_gusbcfg = 0x1417,
61};
62
63int board_usb_init(int index, enum usb_init_type init)
64{
65 int node[2], count;
66 fdt_addr_t addr;
67
68 count = fdtdec_find_aliases_for_id(gd->fdt_blob, "udc",
69 COMPAT_ALTERA_SOCFPGA_DWC2USB,
70 node, 2);
71 if (count <= 0) /* No controller found. */
72 return 0;
73
74 addr = fdtdec_get_addr(gd->fdt_blob, node[0], "reg");
75 if (addr == FDT_ADDR_T_NONE) {
76 printf("UDC Controller has no 'reg' property!\n");
77 return -EINVAL;
78 }
79
80 /* Patch the address from OF into the controller pdata. */
81 socfpga_otg_data.regs_otg = addr;
82
83 return dwc2_udc_probe(&socfpga_otg_data);
84}
85
86int g_dnl_board_usb_cable_connected(void)
87{
88 return 1;
89}
90#endif
Chee Hong Ang7cfcc0c2020-12-24 18:20:56 +080091
92#ifdef CONFIG_SPL_BUILD
93__weak int board_fit_config_name_match(const char *name)
94{
95 /* Just empty function now - can't decide what to choose */
96 debug("%s: %s\n", __func__, name);
97
98 return 0;
99}
100#endif