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wdenkc6097192002-11-03 00:24:07 +00001/*
2 * (C) Copyright 2001, 2002
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 *
23 * This has been changed substantially by Gerald Van Baren, Custom IDEAS,
24 * vanbaren@cideas.com. It was heavily influenced by LiMon, written by
25 * Neil Russell.
26 */
27
28#include <common.h>
29#ifdef CONFIG_MPC8260 /* only valid for MPC8260 */
30#include <ioports.h>
Heiko Schocher7f3afd62008-10-17 13:52:51 +020031#include <asm/io.h>
wdenkc6097192002-11-03 00:24:07 +000032#endif
Ryan Mallon78d66912011-01-27 08:54:15 +130033#if defined(CONFIG_AT91FAMILY)
wdenk20dd2fa2004-11-21 00:06:33 +000034#include <asm/io.h>
35#include <asm/arch/hardware.h>
Jens Scharsiga4db1ca2010-02-03 22:46:58 +010036#include <asm/arch/at91_pio.h>
37#ifdef CONFIG_AT91_LEGACY
Daniel Gorsulowski5a2d8842009-05-18 13:20:54 +020038#include <asm/arch/gpio.h>
Jens Scharsiga4db1ca2010-02-03 22:46:58 +010039#endif
Daniel Gorsulowski5a2d8842009-05-18 13:20:54 +020040#endif
Wolfgang Denk4646d2a2006-05-30 15:56:48 +020041#ifdef CONFIG_IXP425 /* only valid for IXP425 */
42#include <asm/arch/ixp425.h>
43#endif
Peter Pearsed862a252007-05-09 11:37:56 +010044#ifdef CONFIG_LPC2292
45#include <asm/arch/hardware.h>
46#endif
Heiko Schocher643e7c02009-03-12 07:37:34 +010047#if defined(CONFIG_MPC852T) || defined(CONFIG_MPC866)
Heiko Schocher7f3afd62008-10-17 13:52:51 +020048#include <asm/io.h>
49#endif
wdenkc6097192002-11-03 00:24:07 +000050#include <i2c.h>
51
Mike Frysingeree12d542010-07-21 13:38:02 -040052#if defined(CONFIG_SOFT_I2C_GPIO_SCL)
53# include <asm/gpio.h>
54
55# ifndef I2C_GPIO_SYNC
56# define I2C_GPIO_SYNC
57# endif
58
59# ifndef I2C_INIT
60# define I2C_INIT \
61 do { \
62 gpio_request(CONFIG_SOFT_I2C_GPIO_SCL, "soft_i2c"); \
63 gpio_request(CONFIG_SOFT_I2C_GPIO_SDA, "soft_i2c"); \
64 } while (0)
65# endif
66
67# ifndef I2C_ACTIVE
68# define I2C_ACTIVE do { } while (0)
69# endif
70
71# ifndef I2C_TRISTATE
72# define I2C_TRISTATE do { } while (0)
73# endif
74
75# ifndef I2C_READ
76# define I2C_READ gpio_get_value(CONFIG_SOFT_I2C_GPIO_SDA)
77# endif
78
79# ifndef I2C_SDA
80# define I2C_SDA(bit) \
81 do { \
82 if (bit) \
83 gpio_direction_input(CONFIG_SOFT_I2C_GPIO_SDA); \
84 else \
85 gpio_direction_output(CONFIG_SOFT_I2C_GPIO_SDA, 0); \
86 I2C_GPIO_SYNC; \
87 } while (0)
88# endif
89
90# ifndef I2C_SCL
91# define I2C_SCL(bit) \
92 do { \
93 gpio_direction_output(CONFIG_SOFT_I2C_GPIO_SCL, bit); \
94 I2C_GPIO_SYNC; \
95 } while (0)
96# endif
97
98# ifndef I2C_DELAY
99# define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
100# endif
101
102#endif
103
wdenkc6097192002-11-03 00:24:07 +0000104/* #define DEBUG_I2C */
105
Wolfgang Denk6405a152006-03-31 18:32:53 +0200106#ifdef DEBUG_I2C
107DECLARE_GLOBAL_DATA_PTR;
108#endif
109
wdenkc6097192002-11-03 00:24:07 +0000110/*-----------------------------------------------------------------------
111 * Definitions
112 */
113
114#define RETRIES 0
115
wdenkc6097192002-11-03 00:24:07 +0000116#define I2C_ACK 0 /* PD_SDA level to ack a byte */
117#define I2C_NOACK 1 /* PD_SDA level to noack a byte */
118
119
120#ifdef DEBUG_I2C
121#define PRINTD(fmt,args...) do { \
wdenkc6097192002-11-03 00:24:07 +0000122 if (gd->have_console) \
123 printf (fmt ,##args); \
124 } while (0)
125#else
126#define PRINTD(fmt,args...)
127#endif
128
Heiko Schocher9031b212008-10-15 09:34:45 +0200129#if defined(CONFIG_I2C_MULTI_BUS)
Trent Piepho3e9dabd2008-11-12 17:29:48 -0800130static unsigned int i2c_bus_num __attribute__ ((section (".data"))) = 0;
Heiko Schocher9031b212008-10-15 09:34:45 +0200131#endif /* CONFIG_I2C_MULTI_BUS */
132
wdenkc6097192002-11-03 00:24:07 +0000133/*-----------------------------------------------------------------------
134 * Local functions
135 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200136#if !defined(CONFIG_SYS_I2C_INIT_BOARD)
wdenkc6097192002-11-03 00:24:07 +0000137static void send_reset (void);
Heiko Schocher0e2f2c52008-10-15 09:38:38 +0200138#endif
wdenkc6097192002-11-03 00:24:07 +0000139static void send_start (void);
140static void send_stop (void);
141static void send_ack (int);
142static int write_byte (uchar byte);
143static uchar read_byte (int);
144
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200145#if !defined(CONFIG_SYS_I2C_INIT_BOARD)
wdenkc6097192002-11-03 00:24:07 +0000146/*-----------------------------------------------------------------------
147 * Send a reset sequence consisting of 9 clocks with the data signal high
148 * to clock any confused device back into an idle state. Also send a
149 * <stop> at the end of the sequence for belts & suspenders.
150 */
151static void send_reset(void)
152{
Heiko Schocherdc7d22a2008-10-15 09:35:26 +0200153 I2C_SOFT_DECLARATIONS /* intentional without ';' */
wdenkc6097192002-11-03 00:24:07 +0000154 int j;
155
wdenka6db71d2003-04-08 23:25:21 +0000156 I2C_SCL(1);
wdenkc6097192002-11-03 00:24:07 +0000157 I2C_SDA(1);
wdenka6db71d2003-04-08 23:25:21 +0000158#ifdef I2C_INIT
159 I2C_INIT;
160#endif
161 I2C_TRISTATE;
wdenkc6097192002-11-03 00:24:07 +0000162 for(j = 0; j < 9; j++) {
163 I2C_SCL(0);
164 I2C_DELAY;
165 I2C_DELAY;
166 I2C_SCL(1);
167 I2C_DELAY;
168 I2C_DELAY;
169 }
170 send_stop();
171 I2C_TRISTATE;
172}
Heiko Schocher0e2f2c52008-10-15 09:38:38 +0200173#endif
wdenkc6097192002-11-03 00:24:07 +0000174
175/*-----------------------------------------------------------------------
176 * START: High -> Low on SDA while SCL is High
177 */
178static void send_start(void)
179{
Heiko Schocherdc7d22a2008-10-15 09:35:26 +0200180 I2C_SOFT_DECLARATIONS /* intentional without ';' */
wdenkc6097192002-11-03 00:24:07 +0000181
182 I2C_DELAY;
183 I2C_SDA(1);
184 I2C_ACTIVE;
185 I2C_DELAY;
186 I2C_SCL(1);
187 I2C_DELAY;
188 I2C_SDA(0);
189 I2C_DELAY;
190}
191
192/*-----------------------------------------------------------------------
193 * STOP: Low -> High on SDA while SCL is High
194 */
195static void send_stop(void)
196{
Heiko Schocherdc7d22a2008-10-15 09:35:26 +0200197 I2C_SOFT_DECLARATIONS /* intentional without ';' */
wdenkc6097192002-11-03 00:24:07 +0000198
199 I2C_SCL(0);
200 I2C_DELAY;
201 I2C_SDA(0);
202 I2C_ACTIVE;
203 I2C_DELAY;
204 I2C_SCL(1);
205 I2C_DELAY;
206 I2C_SDA(1);
207 I2C_DELAY;
208 I2C_TRISTATE;
209}
210
wdenkc6097192002-11-03 00:24:07 +0000211/*-----------------------------------------------------------------------
212 * ack should be I2C_ACK or I2C_NOACK
213 */
214static void send_ack(int ack)
215{
Heiko Schocherdc7d22a2008-10-15 09:35:26 +0200216 I2C_SOFT_DECLARATIONS /* intentional without ';' */
wdenkc6097192002-11-03 00:24:07 +0000217
wdenkc6097192002-11-03 00:24:07 +0000218 I2C_SCL(0);
219 I2C_DELAY;
wdenkc6097192002-11-03 00:24:07 +0000220 I2C_ACTIVE;
Wolfgang Denkd4a61102006-03-13 00:50:48 +0100221 I2C_SDA(ack);
wdenkc6097192002-11-03 00:24:07 +0000222 I2C_DELAY;
223 I2C_SCL(1);
224 I2C_DELAY;
225 I2C_DELAY;
226 I2C_SCL(0);
227 I2C_DELAY;
228}
229
wdenkc6097192002-11-03 00:24:07 +0000230/*-----------------------------------------------------------------------
231 * Send 8 bits and look for an acknowledgement.
232 */
233static int write_byte(uchar data)
234{
Heiko Schocherdc7d22a2008-10-15 09:35:26 +0200235 I2C_SOFT_DECLARATIONS /* intentional without ';' */
wdenkc6097192002-11-03 00:24:07 +0000236 int j;
237 int nack;
238
239 I2C_ACTIVE;
240 for(j = 0; j < 8; j++) {
241 I2C_SCL(0);
242 I2C_DELAY;
243 I2C_SDA(data & 0x80);
244 I2C_DELAY;
245 I2C_SCL(1);
246 I2C_DELAY;
247 I2C_DELAY;
248
249 data <<= 1;
250 }
251
252 /*
253 * Look for an <ACK>(negative logic) and return it.
254 */
255 I2C_SCL(0);
256 I2C_DELAY;
257 I2C_SDA(1);
258 I2C_TRISTATE;
259 I2C_DELAY;
260 I2C_SCL(1);
261 I2C_DELAY;
262 I2C_DELAY;
263 nack = I2C_READ;
264 I2C_SCL(0);
265 I2C_DELAY;
266 I2C_ACTIVE;
267
268 return(nack); /* not a nack is an ack */
269}
270
Heiko Schocher9031b212008-10-15 09:34:45 +0200271#if defined(CONFIG_I2C_MULTI_BUS)
272/*
273 * Functions for multiple I2C bus handling
274 */
275unsigned int i2c_get_bus_num(void)
276{
277 return i2c_bus_num;
278}
279
280int i2c_set_bus_num(unsigned int bus)
281{
Heiko Schocher6ee861b2008-10-15 09:39:47 +0200282#if defined(CONFIG_I2C_MUX)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200283 if (bus < CONFIG_SYS_MAX_I2C_BUS) {
Heiko Schocher6ee861b2008-10-15 09:39:47 +0200284 i2c_bus_num = bus;
285 } else {
286 int ret;
287
288 ret = i2x_mux_select_mux(bus);
289 if (ret == 0)
290 i2c_bus_num = bus;
291 else
292 return ret;
293 }
294#else
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200295 if (bus >= CONFIG_SYS_MAX_I2C_BUS)
Heiko Schocher9031b212008-10-15 09:34:45 +0200296 return -1;
297 i2c_bus_num = bus;
Heiko Schocher6ee861b2008-10-15 09:39:47 +0200298#endif
Heiko Schocher9031b212008-10-15 09:34:45 +0200299 return 0;
300}
Jens Scharsig7911a922009-03-31 08:18:29 +0200301#endif
Heiko Schocher9031b212008-10-15 09:34:45 +0200302
wdenkc6097192002-11-03 00:24:07 +0000303/*-----------------------------------------------------------------------
304 * if ack == I2C_ACK, ACK the byte so can continue reading, else
305 * send I2C_NOACK to end the read.
306 */
307static uchar read_byte(int ack)
308{
Heiko Schocherdc7d22a2008-10-15 09:35:26 +0200309 I2C_SOFT_DECLARATIONS /* intentional without ';' */
wdenkc6097192002-11-03 00:24:07 +0000310 int data;
311 int j;
312
313 /*
314 * Read 8 bits, MSB first.
315 */
316 I2C_TRISTATE;
Haavard Skinnemoen15fb0a12008-05-16 11:08:11 +0200317 I2C_SDA(1);
wdenkc6097192002-11-03 00:24:07 +0000318 data = 0;
319 for(j = 0; j < 8; j++) {
320 I2C_SCL(0);
321 I2C_DELAY;
322 I2C_SCL(1);
323 I2C_DELAY;
324 data <<= 1;
325 data |= I2C_READ;
326 I2C_DELAY;
327 }
328 send_ack(ack);
329
330 return(data);
331}
332
333/*=====================================================================*/
334/* Public Functions */
335/*=====================================================================*/
336
337/*-----------------------------------------------------------------------
338 * Initialization
339 */
340void i2c_init (int speed, int slaveaddr)
341{
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200342#if defined(CONFIG_SYS_I2C_INIT_BOARD)
Heiko Schocher0e2f2c52008-10-15 09:38:38 +0200343 /* call board specific i2c bus reset routine before accessing the */
344 /* environment, which might be in a chip on that bus. For details */
345 /* about this problem see doc/I2C_Edge_Conditions. */
346 i2c_init_board();
347#else
wdenkc6097192002-11-03 00:24:07 +0000348 /*
wdenk57b2d802003-06-27 21:31:46 +0000349 * WARNING: Do NOT save speed in a static variable: if the
350 * I2C routines are called before RAM is initialized (to read
351 * the DIMM SPD, for instance), RAM won't be usable and your
352 * system will crash.
wdenkc6097192002-11-03 00:24:07 +0000353 */
354 send_reset ();
Heiko Schocher0e2f2c52008-10-15 09:38:38 +0200355#endif
wdenkc6097192002-11-03 00:24:07 +0000356}
357
358/*-----------------------------------------------------------------------
359 * Probe to see if a chip is present. Also good for checking for the
360 * completion of EEPROM writes since the chip stops responding until
361 * the write completes (typically 10mSec).
362 */
363int i2c_probe(uchar addr)
364{
365 int rc;
366
Wolfgang Denk0a8599f2006-03-12 01:30:45 +0100367 /*
Wolfgang Denk2bad8682006-03-12 02:55:22 +0100368 * perform 1 byte write transaction with just address byte
Wolfgang Denk0a8599f2006-03-12 01:30:45 +0100369 * (fake write)
370 */
wdenkc6097192002-11-03 00:24:07 +0000371 send_start();
wdenk34b613e2002-12-17 01:51:00 +0000372 rc = write_byte ((addr << 1) | 0);
wdenkc6097192002-11-03 00:24:07 +0000373 send_stop();
374
375 return (rc ? 1 : 0);
376}
377
378/*-----------------------------------------------------------------------
379 * Read bytes
380 */
381int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
382{
383 int shift;
384 PRINTD("i2c_read: chip %02X addr %02X alen %d buffer %p len %d\n",
385 chip, addr, alen, buffer, len);
386
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200387#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
wdenkc6097192002-11-03 00:24:07 +0000388 /*
389 * EEPROM chips that implement "address overflow" are ones
390 * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
391 * address and the extra bits end up in the "chip address"
392 * bit slots. This makes a 24WC08 (1Kbyte) chip look like
393 * four 256 byte chips.
394 *
395 * Note that we consider the length of the address field to
396 * still be one byte because the extra address bits are
397 * hidden in the chip address.
398 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200399 chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
wdenkc6097192002-11-03 00:24:07 +0000400
401 PRINTD("i2c_read: fix addr_overflow: chip %02X addr %02X\n",
402 chip, addr);
403#endif
404
405 /*
406 * Do the addressing portion of a write cycle to set the
407 * chip's address pointer. If the address length is zero,
408 * don't do the normal write cycle to set the address pointer,
409 * there is no address pointer in this chip.
410 */
411 send_start();
412 if(alen > 0) {
413 if(write_byte(chip << 1)) { /* write cycle */
414 send_stop();
415 PRINTD("i2c_read, no chip responded %02X\n", chip);
416 return(1);
417 }
418 shift = (alen-1) * 8;
419 while(alen-- > 0) {
420 if(write_byte(addr >> shift)) {
421 PRINTD("i2c_read, address not <ACK>ed\n");
422 return(1);
423 }
424 shift -= 8;
425 }
Andrew Dyer58c41f92008-12-29 17:36:01 -0600426
427 /* Some I2C chips need a stop/start sequence here,
428 * other chips don't work with a full stop and need
429 * only a start. Default behaviour is to send the
430 * stop/start sequence.
431 */
432#ifdef CONFIG_SOFT_I2C_READ_REPEATED_START
433 send_start();
434#else
435 send_stop();
wdenkc6097192002-11-03 00:24:07 +0000436 send_start();
Andrew Dyer58c41f92008-12-29 17:36:01 -0600437#endif
wdenkc6097192002-11-03 00:24:07 +0000438 }
439 /*
440 * Send the chip address again, this time for a read cycle.
441 * Then read the data. On the last byte, we do a NACK instead
442 * of an ACK(len == 0) to terminate the read.
443 */
444 write_byte((chip << 1) | 1); /* read cycle */
445 while(len-- > 0) {
446 *buffer++ = read_byte(len == 0);
447 }
448 send_stop();
449 return(0);
450}
451
452/*-----------------------------------------------------------------------
453 * Write bytes
454 */
455int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
456{
457 int shift, failures = 0;
458
459 PRINTD("i2c_write: chip %02X addr %02X alen %d buffer %p len %d\n",
460 chip, addr, alen, buffer, len);
461
462 send_start();
463 if(write_byte(chip << 1)) { /* write cycle */
464 send_stop();
465 PRINTD("i2c_write, no chip responded %02X\n", chip);
466 return(1);
467 }
468 shift = (alen-1) * 8;
469 while(alen-- > 0) {
470 if(write_byte(addr >> shift)) {
471 PRINTD("i2c_write, address not <ACK>ed\n");
472 return(1);
473 }
474 shift -= 8;
475 }
476
477 while(len-- > 0) {
478 if(write_byte(*buffer++)) {
479 failures++;
480 }
481 }
482 send_stop();
483 return(failures);
484}