| Michal Simek | 59aadc5 | 2019-04-08 13:43:51 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
| 2 | /* |
| Sandeep Gundlupet Raju | 99006eb | 2021-11-30 13:56:58 +0100 | [diff] [blame] | 3 | * Copyright (C) 2019 - 2021 Xilinx, Inc. |
| Michal Simek | 59aadc5 | 2019-04-08 13:43:51 +0200 | [diff] [blame] | 4 | */ |
| 5 | |
| 6 | #ifndef _DT_BINDINGS_VERSAL_POWER_H |
| 7 | #define _DT_BINDINGS_VERSAL_POWER_H |
| 8 | |
| Michal Simek | 6ab01ca | 2022-03-30 09:56:23 +0200 | [diff] [blame] | 9 | #define PM_DEV_RPU0_0 (0x18110005U) |
| 10 | #define PM_DEV_RPU0_1 (0x18110006U) |
| 11 | #define PM_DEV_OCM_0 (0x18314007U) |
| 12 | #define PM_DEV_OCM_1 (0x18314008U) |
| 13 | #define PM_DEV_OCM_2 (0x18314009U) |
| 14 | #define PM_DEV_OCM_3 (0x1831400aU) |
| 15 | #define PM_DEV_TCM_0_A (0x1831800bU) |
| 16 | #define PM_DEV_TCM_0_B (0x1831800cU) |
| 17 | #define PM_DEV_TCM_1_A (0x1831800dU) |
| 18 | #define PM_DEV_TCM_1_B (0x1831800eU) |
| Michal Simek | 59aadc5 | 2019-04-08 13:43:51 +0200 | [diff] [blame] | 19 | #define PM_DEV_USB_0 (0x18224018U) |
| 20 | #define PM_DEV_GEM_0 (0x18224019U) |
| 21 | #define PM_DEV_GEM_1 (0x1822401aU) |
| 22 | #define PM_DEV_SPI_0 (0x1822401bU) |
| 23 | #define PM_DEV_SPI_1 (0x1822401cU) |
| 24 | #define PM_DEV_I2C_0 (0x1822401dU) |
| 25 | #define PM_DEV_I2C_1 (0x1822401eU) |
| 26 | #define PM_DEV_CAN_FD_0 (0x1822401fU) |
| 27 | #define PM_DEV_CAN_FD_1 (0x18224020U) |
| 28 | #define PM_DEV_UART_0 (0x18224021U) |
| 29 | #define PM_DEV_UART_1 (0x18224022U) |
| 30 | #define PM_DEV_GPIO (0x18224023U) |
| 31 | #define PM_DEV_TTC_0 (0x18224024U) |
| 32 | #define PM_DEV_TTC_1 (0x18224025U) |
| 33 | #define PM_DEV_TTC_2 (0x18224026U) |
| 34 | #define PM_DEV_TTC_3 (0x18224027U) |
| 35 | #define PM_DEV_SWDT_FPD (0x18224029U) |
| 36 | #define PM_DEV_OSPI (0x1822402aU) |
| 37 | #define PM_DEV_QSPI (0x1822402bU) |
| 38 | #define PM_DEV_GPIO_PMC (0x1822402cU) |
| Sandeep Gundlupet Raju | 99006eb | 2021-11-30 13:56:58 +0100 | [diff] [blame] | 39 | #define PM_DEV_I2C_PMC (0x1822402dU) |
| Michal Simek | 59aadc5 | 2019-04-08 13:43:51 +0200 | [diff] [blame] | 40 | #define PM_DEV_SDIO_0 (0x1822402eU) |
| 41 | #define PM_DEV_SDIO_1 (0x1822402fU) |
| 42 | #define PM_DEV_RTC (0x18224034U) |
| 43 | #define PM_DEV_ADMA_0 (0x18224035U) |
| 44 | #define PM_DEV_ADMA_1 (0x18224036U) |
| 45 | #define PM_DEV_ADMA_2 (0x18224037U) |
| 46 | #define PM_DEV_ADMA_3 (0x18224038U) |
| 47 | #define PM_DEV_ADMA_4 (0x18224039U) |
| 48 | #define PM_DEV_ADMA_5 (0x1822403aU) |
| 49 | #define PM_DEV_ADMA_6 (0x1822403bU) |
| 50 | #define PM_DEV_ADMA_7 (0x1822403cU) |
| Michal Simek | 6ab01ca | 2022-03-30 09:56:23 +0200 | [diff] [blame] | 51 | #define PM_DEV_AMS_ROOT (0x18224055U) |
| Michal Simek | 59aadc5 | 2019-04-08 13:43:51 +0200 | [diff] [blame] | 52 | #define PM_DEV_AI (0x18224072U) |
| 53 | |
| 54 | #endif |