Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0 |
Simon Glass | e7d04d8 | 2016-03-11 22:07:19 -0700 | [diff] [blame] | 2 | /* |
| 3 | * Copyright (c) 2016 Google, Inc |
Simon Glass | e7d04d8 | 2016-03-11 22:07:19 -0700 | [diff] [blame] | 4 | */ |
| 5 | |
| 6 | #include <common.h> |
| 7 | #include <dm.h> |
| 8 | #include <pch.h> |
| 9 | #include <asm/cpu.h> |
| 10 | #include <asm/gpio.h> |
| 11 | #include <asm/i8259.h> |
| 12 | #include <asm/intel_regs.h> |
| 13 | #include <asm/io.h> |
| 14 | #include <asm/ioapic.h> |
| 15 | #include <asm/lpc_common.h> |
| 16 | #include <asm/pch_common.h> |
| 17 | #include <asm/arch/cpu.h> |
| 18 | #include <asm/arch/gpio.h> |
| 19 | #include <asm/arch/iomap.h> |
| 20 | #include <asm/arch/pch.h> |
| 21 | #include <asm/arch/pm.h> |
| 22 | #include <asm/arch/rcb.h> |
Simon Glass | 3642ba9 | 2019-02-16 20:25:03 -0700 | [diff] [blame] | 23 | #include <asm/arch/serialio.h> |
Simon Glass | e7d04d8 | 2016-03-11 22:07:19 -0700 | [diff] [blame] | 24 | #include <asm/arch/spi.h> |
Simon Glass | 3642ba9 | 2019-02-16 20:25:03 -0700 | [diff] [blame] | 25 | #include <dm/uclass-internal.h> |
Simon Glass | e7d04d8 | 2016-03-11 22:07:19 -0700 | [diff] [blame] | 26 | |
| 27 | #define BIOS_CTRL 0xdc |
| 28 | |
| 29 | bool cpu_is_ult(void) |
| 30 | { |
| 31 | u32 fm = cpu_get_family_model(); |
| 32 | |
| 33 | return fm == BROADWELL_FAMILY_ULT || fm == HASWELL_FAMILY_ULT; |
| 34 | } |
| 35 | |
| 36 | static int broadwell_pch_early_init(struct udevice *dev) |
| 37 | { |
| 38 | struct gpio_desc desc; |
| 39 | struct udevice *bus; |
| 40 | pci_dev_t bdf; |
| 41 | int ret; |
| 42 | |
| 43 | dm_pci_write_config32(dev, PCH_RCBA, RCB_BASE_ADDRESS | 1); |
| 44 | |
| 45 | dm_pci_write_config32(dev, PMBASE, ACPI_BASE_ADDRESS | 1); |
| 46 | dm_pci_write_config8(dev, ACPI_CNTL, ACPI_EN); |
| 47 | dm_pci_write_config32(dev, GPIO_BASE, GPIO_BASE_ADDRESS | 1); |
| 48 | dm_pci_write_config8(dev, GPIO_CNTL, GPIO_EN); |
| 49 | |
| 50 | /* Enable IOAPIC */ |
| 51 | writew(0x1000, RCB_REG(OIC)); |
| 52 | /* Read back for posted write */ |
| 53 | readw(RCB_REG(OIC)); |
| 54 | |
| 55 | /* Set HPET address and enable it */ |
| 56 | clrsetbits_le32(RCB_REG(HPTC), 3, 1 << 7); |
| 57 | /* Read back for posted write */ |
| 58 | readl(RCB_REG(HPTC)); |
| 59 | /* Enable HPET to start counter */ |
| 60 | setbits_le32(HPET_BASE_ADDRESS + 0x10, 1 << 0); |
| 61 | |
| 62 | setbits_le32(RCB_REG(GCS), 1 << 5); |
| 63 | |
| 64 | /* |
| 65 | * Enable PP3300_AUTOBAHN_EN after initial GPIO setup |
| 66 | * to prevent possible brownout. This will cause the GPIOs to be set |
| 67 | * up if it has not been done already. |
| 68 | */ |
| 69 | ret = gpio_request_by_name(dev, "power-enable-gpio", 0, &desc, |
| 70 | GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE); |
| 71 | if (ret) |
| 72 | return ret; |
| 73 | |
| 74 | /* 8.14 Additional PCI Express Programming Steps, step #1 */ |
| 75 | bdf = PCI_BDF(0, 0x1c, 0); |
| 76 | bus = pci_get_controller(dev); |
| 77 | pci_bus_clrset_config32(bus, bdf, 0xf4, 0x60, 0); |
| 78 | pci_bus_clrset_config32(bus, bdf, 0xf4, 0x80, 0x80); |
| 79 | pci_bus_clrset_config32(bus, bdf, 0xe2, 0x30, 0x30); |
| 80 | |
| 81 | return 0; |
| 82 | } |
| 83 | |
| 84 | static void pch_misc_init(struct udevice *dev) |
| 85 | { |
| 86 | /* Setup SLP signal assertion, SLP_S4=4s, SLP_S3=50ms */ |
| 87 | dm_pci_clrset_config8(dev, GEN_PMCON_3, 3 << 4 | 1 << 10, |
| 88 | 1 << 3 | 1 << 11 | 1 << 12); |
| 89 | /* Prepare sleep mode */ |
| 90 | clrsetio_32(ACPI_BASE_ADDRESS + PM1_CNT, SLP_TYP, SCI_EN); |
| 91 | |
| 92 | /* Setup NMI on errors, disable SERR */ |
| 93 | clrsetio_8(0x61, 0xf0, 1 << 2); |
| 94 | /* Disable NMI sources */ |
| 95 | setio_8(0x70, 1 << 7); |
| 96 | /* Indicate DRAM init done for MRC */ |
| 97 | dm_pci_clrset_config8(dev, GEN_PMCON_2, 0, 1 << 7); |
| 98 | |
| 99 | /* Clear status bits to prevent unexpected wake */ |
| 100 | setbits_le32(RCB_REG(0x3310), 0x0000002f); |
| 101 | clrsetbits_le32(RCB_REG(0x3f02), 0x0000000f, 0); |
| 102 | /* Enable PCIe Relaxed Order */ |
| 103 | setbits_le32(RCB_REG(0x2314), 1 << 31 | 1 << 7); |
| 104 | setbits_le32(RCB_REG(0x1114), 1 << 15 | 1 << 14); |
| 105 | /* Setup SERIRQ, enable continuous mode */ |
| 106 | dm_pci_clrset_config8(dev, SERIRQ_CNTL, 0, 1 << 7 | 1 << 6); |
| 107 | }; |
| 108 | |
| 109 | static void pch_enable_ioapic(void) |
| 110 | { |
| 111 | u32 reg32; |
| 112 | |
Bin Meng | ff0c478 | 2016-05-22 01:45:35 -0700 | [diff] [blame] | 113 | /* Make sure this is a unique ID within system */ |
| 114 | io_apic_set_id(0x04); |
Simon Glass | e7d04d8 | 2016-03-11 22:07:19 -0700 | [diff] [blame] | 115 | |
| 116 | /* affirm full set of redirection table entries ("write once") */ |
| 117 | reg32 = io_apic_read(0x01); |
| 118 | |
| 119 | /* PCH-LP has 39 redirection entries */ |
| 120 | reg32 &= ~0x00ff0000; |
| 121 | reg32 |= 0x00270000; |
| 122 | |
| 123 | io_apic_write(0x01, reg32); |
| 124 | |
| 125 | /* |
| 126 | * Select Boot Configuration register (0x03) and |
| 127 | * use Processor System Bus (0x01) to deliver interrupts. |
| 128 | */ |
| 129 | io_apic_write(0x03, 0x01); |
| 130 | } |
| 131 | |
| 132 | /* Enable all requested GPE */ |
| 133 | void enable_all_gpe(u32 set1, u32 set2, u32 set3, u32 set4) |
| 134 | { |
| 135 | outl(set1, ACPI_BASE_ADDRESS + GPE0_EN(GPE_31_0)); |
| 136 | outl(set2, ACPI_BASE_ADDRESS + GPE0_EN(GPE_63_32)); |
| 137 | outl(set3, ACPI_BASE_ADDRESS + GPE0_EN(GPE_94_64)); |
| 138 | outl(set4, ACPI_BASE_ADDRESS + GPE0_EN(GPE_STD)); |
| 139 | } |
| 140 | |
| 141 | /* |
| 142 | * Enable GPIO SMI events - it would be good to put this in the GPIO driver |
| 143 | * but it would need a new driver operation. |
| 144 | */ |
| 145 | int enable_alt_smi(struct udevice *pch, u32 mask) |
| 146 | { |
| 147 | struct pch_lp_gpio_regs *regs; |
| 148 | u32 gpiobase; |
| 149 | int ret; |
| 150 | |
| 151 | ret = pch_get_gpio_base(pch, &gpiobase); |
| 152 | if (ret) { |
| 153 | debug("%s: invalid GPIOBASE address (%08x)\n", __func__, |
| 154 | gpiobase); |
| 155 | return -EINVAL; |
| 156 | } |
| 157 | |
| 158 | regs = (struct pch_lp_gpio_regs *)gpiobase; |
| 159 | setio_32(regs->alt_gpi_smi_en, mask); |
| 160 | |
| 161 | return 0; |
| 162 | } |
| 163 | |
| 164 | static int pch_power_options(struct udevice *dev) |
| 165 | { |
| 166 | int pwr_on_after_power_fail = MAINBOARD_POWER_OFF; |
| 167 | const char *state; |
| 168 | u32 enable[4]; |
| 169 | u16 reg16; |
| 170 | int ret; |
| 171 | |
| 172 | dm_pci_read_config16(dev, GEN_PMCON_3, ®16); |
| 173 | reg16 &= 0xfffe; |
| 174 | switch (pwr_on_after_power_fail) { |
| 175 | case MAINBOARD_POWER_OFF: |
| 176 | reg16 |= 1; |
| 177 | state = "off"; |
| 178 | break; |
| 179 | case MAINBOARD_POWER_ON: |
| 180 | reg16 &= ~1; |
| 181 | state = "on"; |
| 182 | break; |
| 183 | case MAINBOARD_POWER_KEEP: |
| 184 | reg16 &= ~1; |
| 185 | state = "state keep"; |
| 186 | break; |
| 187 | default: |
| 188 | state = "undefined"; |
| 189 | } |
| 190 | dm_pci_write_config16(dev, GEN_PMCON_3, reg16); |
| 191 | debug("Set power %s after power failure.\n", state); |
| 192 | |
| 193 | /* GPE setup based on device tree configuration */ |
Simon Glass | dd79d6e | 2017-01-17 16:52:55 -0700 | [diff] [blame] | 194 | ret = fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(dev), |
Simon Glass | e7d04d8 | 2016-03-11 22:07:19 -0700 | [diff] [blame] | 195 | "intel,gpe0-en", enable, ARRAY_SIZE(enable)); |
| 196 | if (ret) |
| 197 | return -EINVAL; |
| 198 | enable_all_gpe(enable[0], enable[1], enable[2], enable[3]); |
| 199 | |
| 200 | /* SMI setup based on device tree configuration */ |
Simon Glass | dd79d6e | 2017-01-17 16:52:55 -0700 | [diff] [blame] | 201 | enable_alt_smi(dev, fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), |
Simon Glass | e7d04d8 | 2016-03-11 22:07:19 -0700 | [diff] [blame] | 202 | "intel,alt-gp-smi-enable", 0)); |
| 203 | |
| 204 | return 0; |
| 205 | } |
| 206 | |
| 207 | /* Magic register settings for power management */ |
| 208 | static void pch_pm_init_magic(struct udevice *dev) |
| 209 | { |
| 210 | dm_pci_write_config8(dev, 0xa9, 0x46); |
| 211 | clrbits_le32(RCB_REG(0x232c), 1), |
| 212 | setbits_le32(RCB_REG(0x1100), 0x0000c13f); |
| 213 | clrsetbits_le32(RCB_REG(0x2320), 0x60, 0x10); |
| 214 | writel(0x00012fff, RCB_REG(0x3314)); |
| 215 | clrsetbits_le32(RCB_REG(0x3318), 0x000f0330, 0x0dcf0400); |
| 216 | writel(0x04000000, RCB_REG(0x3324)); |
| 217 | writel(0x00041400, RCB_REG(0x3368)); |
| 218 | writel(0x3f8ddbff, RCB_REG(0x3388)); |
| 219 | writel(0x00007001, RCB_REG(0x33ac)); |
| 220 | writel(0x00181900, RCB_REG(0x33b0)); |
| 221 | writel(0x00060A00, RCB_REG(0x33c0)); |
| 222 | writel(0x06200840, RCB_REG(0x33d0)); |
| 223 | writel(0x01010101, RCB_REG(0x3a28)); |
| 224 | writel(0x040c0404, RCB_REG(0x3a2c)); |
| 225 | writel(0x9000000a, RCB_REG(0x3a9c)); |
| 226 | writel(0x03808033, RCB_REG(0x2b1c)); |
| 227 | writel(0x80000009, RCB_REG(0x2b34)); |
| 228 | writel(0x022ddfff, RCB_REG(0x3348)); |
| 229 | writel(0x00000001, RCB_REG(0x334c)); |
| 230 | writel(0x0001c000, RCB_REG(0x3358)); |
| 231 | writel(0x3f8ddbff, RCB_REG(0x3380)); |
| 232 | writel(0x0001c7e1, RCB_REG(0x3384)); |
| 233 | writel(0x0001c7e1, RCB_REG(0x338c)); |
| 234 | writel(0x0001c000, RCB_REG(0x3398)); |
| 235 | writel(0x00181900, RCB_REG(0x33a8)); |
| 236 | writel(0x00080000, RCB_REG(0x33dc)); |
| 237 | writel(0x00000001, RCB_REG(0x33e0)); |
| 238 | writel(0x0000040c, RCB_REG(0x3a20)); |
| 239 | writel(0x01010101, RCB_REG(0x3a24)); |
| 240 | writel(0x01010101, RCB_REG(0x3a30)); |
| 241 | dm_pci_clrset_config32(dev, 0xac, 0x00200000, 0); |
| 242 | setbits_le32(RCB_REG(0x0410), 0x00000003); |
| 243 | setbits_le32(RCB_REG(0x2618), 0x08000000); |
| 244 | setbits_le32(RCB_REG(0x2300), 0x00000002); |
| 245 | setbits_le32(RCB_REG(0x2600), 0x00000008); |
| 246 | writel(0x00007001, RCB_REG(0x33b4)); |
| 247 | writel(0x022ddfff, RCB_REG(0x3350)); |
| 248 | writel(0x00000001, RCB_REG(0x3354)); |
| 249 | /* Power Optimizer */ |
| 250 | setbits_le32(RCB_REG(0x33d4), 0x08000000); |
| 251 | /* |
| 252 | * This stops the LCD from turning on: |
| 253 | * setbits_le32(RCB_REG(0x33c8), 0x08000080); |
| 254 | */ |
| 255 | writel(0x0000883c, RCB_REG(0x2b10)); |
| 256 | writel(0x1e0a4616, RCB_REG(0x2b14)); |
| 257 | writel(0x40000005, RCB_REG(0x2b24)); |
| 258 | writel(0x0005db01, RCB_REG(0x2b20)); |
| 259 | writel(0x05145005, RCB_REG(0x3a80)); |
| 260 | writel(0x00001005, RCB_REG(0x3a84)); |
| 261 | setbits_le32(RCB_REG(0x33d4), 0x2fff2fb1); |
| 262 | setbits_le32(RCB_REG(0x33c8), 0x00008000); |
| 263 | }; |
| 264 | |
| 265 | static int pch_type(struct udevice *dev) |
| 266 | { |
| 267 | u16 type; |
| 268 | |
| 269 | dm_pci_read_config16(dev, PCI_DEVICE_ID, &type); |
| 270 | |
| 271 | return type; |
| 272 | } |
| 273 | |
| 274 | /* Return 1 if PCH type is WildcatPoint */ |
| 275 | static int pch_is_wpt(struct udevice *dev) |
| 276 | { |
| 277 | return ((pch_type(dev) & 0xfff0) == 0x9cc0) ? 1 : 0; |
| 278 | } |
| 279 | |
| 280 | /* Return 1 if PCH type is WildcatPoint ULX */ |
| 281 | static int pch_is_wpt_ulx(struct udevice *dev) |
| 282 | { |
| 283 | u16 lpcid = pch_type(dev); |
| 284 | |
| 285 | switch (lpcid) { |
| 286 | case PCH_WPT_BDW_Y_SAMPLE: |
| 287 | case PCH_WPT_BDW_Y_PREMIUM: |
| 288 | case PCH_WPT_BDW_Y_BASE: |
| 289 | return 1; |
| 290 | } |
| 291 | |
| 292 | return 0; |
| 293 | } |
| 294 | |
| 295 | static u32 pch_read_soft_strap(int id) |
| 296 | { |
| 297 | clrbits_le32(SPI_REG(SPIBAR_FDOC), 0x00007ffc); |
| 298 | setbits_le32(SPI_REG(SPIBAR_FDOC), 0x00004000 | id * 4); |
| 299 | |
| 300 | return readl(SPI_REG(SPIBAR_FDOD)); |
| 301 | } |
| 302 | |
| 303 | static void pch_enable_mphy(struct udevice *dev) |
| 304 | { |
| 305 | u32 data_and = 0xffffffff; |
| 306 | u32 data_or = (1 << 14) | (1 << 13) | (1 << 12); |
| 307 | |
| 308 | data_or |= (1 << 0); |
| 309 | if (pch_is_wpt(dev)) { |
| 310 | data_and &= ~((1 << 7) | (1 << 6) | (1 << 3)); |
| 311 | data_or |= (1 << 5) | (1 << 4); |
| 312 | |
| 313 | if (pch_is_wpt_ulx(dev)) { |
| 314 | /* Check if SATA and USB3 MPHY are enabled */ |
| 315 | u32 strap19 = pch_read_soft_strap(19); |
| 316 | strap19 &= ((1 << 31) | (1 << 30)); |
| 317 | strap19 >>= 30; |
| 318 | if (strap19 == 3) { |
| 319 | data_or |= (1 << 3); |
| 320 | debug("Enable ULX MPHY PG control in single domain\n"); |
| 321 | } else if (strap19 == 0) { |
| 322 | debug("Enable ULX MPHY PG control in split domains\n"); |
| 323 | } else { |
| 324 | debug("Invalid PCH Soft Strap 19 configuration\n"); |
| 325 | } |
| 326 | } else { |
| 327 | data_or |= (1 << 3); |
| 328 | } |
| 329 | } |
| 330 | |
| 331 | pch_iobp_update(0xCF000000, data_and, data_or); |
| 332 | } |
| 333 | |
| 334 | static void pch_init_deep_sx(bool deep_sx_enable_ac, bool deep_sx_enable_dc) |
| 335 | { |
| 336 | if (deep_sx_enable_ac) { |
| 337 | setbits_le32(RCB_REG(DEEP_S3_POL), DEEP_S3_EN_AC); |
| 338 | setbits_le32(RCB_REG(DEEP_S5_POL), DEEP_S5_EN_AC); |
| 339 | } |
| 340 | |
| 341 | if (deep_sx_enable_dc) { |
| 342 | setbits_le32(RCB_REG(DEEP_S3_POL), DEEP_S3_EN_DC); |
| 343 | setbits_le32(RCB_REG(DEEP_S5_POL), DEEP_S5_EN_DC); |
| 344 | } |
| 345 | |
| 346 | if (deep_sx_enable_ac || deep_sx_enable_dc) { |
| 347 | setbits_le32(RCB_REG(DEEP_SX_CONFIG), |
| 348 | DEEP_SX_WAKE_PIN_EN | DEEP_SX_GP27_PIN_EN); |
| 349 | } |
| 350 | } |
| 351 | |
| 352 | /* Power Management init */ |
| 353 | static void pch_pm_init(struct udevice *dev) |
| 354 | { |
| 355 | debug("PCH PM init\n"); |
| 356 | |
| 357 | pch_init_deep_sx(false, false); |
| 358 | pch_enable_mphy(dev); |
| 359 | pch_pm_init_magic(dev); |
| 360 | |
| 361 | if (pch_is_wpt(dev)) { |
| 362 | setbits_le32(RCB_REG(0x33e0), 1 << 4 | 1 << 1); |
| 363 | setbits_le32(RCB_REG(0x2b1c), 1 << 22 | 1 << 14 | 1 << 13); |
| 364 | writel(0x16bf0002, RCB_REG(0x33e4)); |
| 365 | setbits_le32(RCB_REG(0x33e4), 0x1); |
| 366 | } |
| 367 | |
| 368 | pch_iobp_update(0xCA000000, ~0UL, 0x00000009); |
| 369 | |
| 370 | /* Set RCBA 0x2b1c[29]=1 if DSP disabled */ |
| 371 | if (readl(RCB_REG(FD)) & PCH_DISABLE_ADSPD) |
| 372 | setbits_le32(RCB_REG(0x2b1c), 1 << 29); |
| 373 | } |
| 374 | |
| 375 | static void pch_cg_init(struct udevice *dev) |
| 376 | { |
| 377 | struct udevice *bus = pci_get_controller(dev); |
| 378 | u32 reg32; |
| 379 | u16 reg16; |
| 380 | ulong val; |
| 381 | |
| 382 | /* DMI */ |
| 383 | setbits_le32(RCB_REG(0x2234), 0xf); |
| 384 | |
| 385 | dm_pci_read_config16(dev, GEN_PMCON_1, ®16); |
| 386 | reg16 &= ~(1 << 10); /* Disable BIOS_PCI_EXP_EN for native PME */ |
| 387 | if (pch_is_wpt(dev)) |
| 388 | reg16 &= ~(1 << 11); |
| 389 | else |
| 390 | reg16 |= 1 << 11; |
| 391 | reg16 |= 1 << 5 | 1 << 6 | 1 << 7 | 1 << 12; |
| 392 | reg16 |= 1 << 2; /* PCI CLKRUN# Enable */ |
| 393 | dm_pci_write_config16(dev, GEN_PMCON_1, reg16); |
| 394 | |
| 395 | /* |
| 396 | * RCBA + 0x2614[27:25,14:13,10,8] = 101,11,1,1 |
| 397 | * RCBA + 0x2614[23:16] = 0x20 |
| 398 | * RCBA + 0x2614[30:28] = 0x0 |
| 399 | * RCBA + 0x2614[26] = 1 (IF 0:2.0@0x08 >= 0x0b) |
| 400 | */ |
| 401 | clrsetbits_le32(RCB_REG(0x2614), 0x64ff0000, 0x0a206500); |
| 402 | |
| 403 | /* Check for 0:2.0@0x08 >= 0x0b */ |
| 404 | pci_bus_read_config(bus, PCI_BDF(0, 0x2, 0), 0x8, &val, PCI_SIZE_8); |
| 405 | if (pch_is_wpt(dev) || val >= 0x0b) |
| 406 | setbits_le32(RCB_REG(0x2614), 1 << 26); |
| 407 | |
| 408 | setbits_le32(RCB_REG(0x900), 0x0000031f); |
| 409 | |
| 410 | reg32 = readl(RCB_REG(CG)); |
| 411 | if (readl(RCB_REG(0x3454)) & (1 << 4)) |
| 412 | reg32 &= ~(1 << 29); /* LPC Dynamic */ |
| 413 | else |
| 414 | reg32 |= (1 << 29); /* LPC Dynamic */ |
| 415 | reg32 |= 1 << 31; /* LP LPC */ |
| 416 | reg32 |= 1 << 30; /* LP BLA */ |
| 417 | if (readl(RCB_REG(0x3454)) & (1 << 4)) |
| 418 | reg32 &= ~(1 << 29); |
| 419 | else |
| 420 | reg32 |= 1 << 29; |
| 421 | reg32 |= 1 << 28; /* GPIO Dynamic */ |
| 422 | reg32 |= 1 << 27; /* HPET Dynamic */ |
| 423 | reg32 |= 1 << 26; /* Generic Platform Event Clock */ |
| 424 | if (readl(RCB_REG(BUC)) & PCH_DISABLE_GBE) |
| 425 | reg32 |= 1 << 23; /* GbE Static */ |
| 426 | if (readl(RCB_REG(FD)) & PCH_DISABLE_HD_AUDIO) |
| 427 | reg32 |= 1 << 21; /* HDA Static */ |
| 428 | reg32 |= 1 << 22; /* HDA Dynamic */ |
| 429 | writel(reg32, RCB_REG(CG)); |
| 430 | |
| 431 | /* PCH-LP LPC */ |
| 432 | if (pch_is_wpt(dev)) |
| 433 | clrsetbits_le32(RCB_REG(0x3434), 0x1f, 0x17); |
| 434 | else |
| 435 | setbits_le32(RCB_REG(0x3434), 0x7); |
| 436 | |
| 437 | /* SPI */ |
| 438 | setbits_le32(RCB_REG(0x38c0), 0x3c07); |
| 439 | |
| 440 | pch_iobp_update(0xCE00C000, ~1UL, 0x00000000); |
| 441 | } |
| 442 | |
| 443 | static void systemagent_init(void) |
| 444 | { |
| 445 | /* Enable Power Aware Interrupt Routing */ |
| 446 | clrsetbits_8(MCHBAR_REG(MCH_PAIR), 0x7, 0x4); /* Fixed Priority */ |
| 447 | |
| 448 | /* |
| 449 | * Set bits 0+1 of BIOS_RESET_CPL to indicate to the CPU |
| 450 | * that BIOS has initialized memory and power management |
| 451 | */ |
| 452 | setbits_8(MCHBAR_REG(BIOS_RESET_CPL), 3); |
| 453 | debug("Set BIOS_RESET_CPL\n"); |
| 454 | |
| 455 | /* Configure turbo power limits 1ms after reset complete bit */ |
| 456 | mdelay(1); |
| 457 | |
| 458 | cpu_set_power_limits(28); |
| 459 | } |
| 460 | |
Simon Glass | 3642ba9 | 2019-02-16 20:25:03 -0700 | [diff] [blame] | 461 | /* Enable LTR Auto Mode for D21:F1-F6 */ |
| 462 | static void serialio_d21_ltr(u32 bar0) |
| 463 | { |
| 464 | /* 1. Program BAR0 + 808h[2] = 0b */ |
| 465 | clrbits_le32(bar0 + SIO_REG_PPR_GEN, SIO_REG_PPR_GEN_LTR_MODE_MASK); |
| 466 | |
| 467 | /* 2. Program BAR0 + 804h[1:0] = 00b */ |
| 468 | clrbits_le32(bar0 + SIO_REG_PPR_RST, SIO_REG_PPR_RST_ASSERT); |
| 469 | |
| 470 | /* 3. Program BAR0 + 804h[1:0] = 11b */ |
| 471 | setbits_le32(bar0 + SIO_REG_PPR_RST, SIO_REG_PPR_RST_ASSERT); |
| 472 | |
| 473 | /* 4. Program BAR0 + 814h[31:0] = 00000000h */ |
| 474 | writel(0, bar0 + SIO_REG_AUTO_LTR); |
| 475 | } |
| 476 | |
| 477 | /* Select I2C voltage of 1.8V or 3.3V */ |
| 478 | static void serialio_i2c_voltage_sel(u32 bar0, uint voltage) |
| 479 | { |
| 480 | clrsetbits_le32(bar0 + SIO_REG_PPR_GEN, SIO_REG_PPR_GEN_VOLTAGE_MASK, |
| 481 | SIO_REG_PPR_GEN_VOLTAGE(voltage)); |
| 482 | } |
| 483 | |
| 484 | /* Put Serial IO D21:F0-F6 device into desired mode */ |
| 485 | static void serialio_d21_mode(int sio_index, int int_pin, bool acpi_mode) |
| 486 | { |
| 487 | u32 portctrl = SIO_IOBP_PORTCTRL_PM_CAP_PRSNT; |
| 488 | |
| 489 | /* Snoop select 1 */ |
| 490 | portctrl |= SIO_IOBP_PORTCTRL_SNOOP_SELECT(1); |
| 491 | |
| 492 | /* Set interrupt pin */ |
| 493 | portctrl |= SIO_IOBP_PORTCTRL_INT_PIN(int_pin); |
| 494 | |
| 495 | if (acpi_mode) { |
| 496 | /* Enable ACPI interrupt mode */ |
| 497 | portctrl |= SIO_IOBP_PORTCTRL_ACPI_IRQ_EN; |
| 498 | } |
| 499 | |
| 500 | pch_iobp_update(SIO_IOBP_PORTCTRLX(sio_index), 0, portctrl); |
| 501 | } |
| 502 | |
| 503 | /* Init sequence to be run once, done as part of D21:F0 (SDMA) init */ |
| 504 | static void serialio_init_once(bool acpi_mode) |
| 505 | { |
| 506 | if (acpi_mode) { |
| 507 | /* Enable ACPI IRQ for IRQ13, IRQ7, IRQ6, IRQ5 in RCBA */ |
| 508 | setbits_le32(RCB_REG(ACPIIRQEN), |
| 509 | 1 << 13 | 1 << 7 | 1 << 6 | 1 << 5); |
| 510 | } |
| 511 | |
| 512 | /* Program IOBP CB000154h[12,9:8,4:0] = 1001100011111b */ |
| 513 | pch_iobp_update(SIO_IOBP_GPIODF, ~0x0000131f, 0x0000131f); |
| 514 | |
| 515 | /* Program IOBP CB000180h[5:0] = 111111b (undefined register) */ |
| 516 | pch_iobp_update(0xcb000180, ~0x0000003f, 0x0000003f); |
| 517 | } |
| 518 | |
| 519 | /** |
| 520 | * pch_serialio_init() - set up serial I/O devices |
| 521 | * |
| 522 | * @return 0 if OK, -ve on error |
| 523 | */ |
| 524 | static int pch_serialio_init(void) |
| 525 | { |
| 526 | struct udevice *dev, *hda; |
| 527 | bool acpi_mode = true; |
| 528 | u32 bar0, bar1; |
| 529 | int ret; |
| 530 | |
| 531 | ret = uclass_find_first_device(UCLASS_I2C, &dev); |
| 532 | if (ret) |
| 533 | return ret; |
| 534 | bar0 = dm_pci_read_bar32(dev, 0); |
| 535 | if (!bar0) |
| 536 | return -EINVAL; |
| 537 | bar1 = dm_pci_read_bar32(dev, 1); |
| 538 | if (!bar1) |
| 539 | return -EINVAL; |
| 540 | |
| 541 | serialio_init_once(acpi_mode); |
| 542 | serialio_d21_mode(SIO_ID_SDMA, SIO_PIN_INTB, acpi_mode); |
| 543 | |
| 544 | serialio_d21_ltr(bar0); |
| 545 | serialio_i2c_voltage_sel(bar0, 1); /* Select 1.8V always */ |
| 546 | serialio_d21_mode(SIO_ID_I2C0, SIO_PIN_INTC, acpi_mode); |
| 547 | setbits_le32(bar1 + PCH_PCS, PCH_PCS_PS_D3HOT); |
| 548 | |
| 549 | clrbits_le32(bar1 + PCH_PCS, PCH_PCS_PS_D3HOT); |
| 550 | |
| 551 | setbits_le32(bar0 + SIO_REG_PPR_CLOCK, SIO_REG_PPR_CLOCK_EN); |
| 552 | |
| 553 | /* Manually find the High-definition audio, to turn it off */ |
| 554 | ret = dm_pci_bus_find_bdf(PCI_BDF(0, 0x1b, 0), &hda); |
| 555 | if (ret) |
| 556 | return -ENOENT; |
| 557 | dm_pci_clrset_config8(hda, 0x43, 0, 0x6f); |
| 558 | |
| 559 | /* Route I/O buffers to ADSP function */ |
| 560 | dm_pci_clrset_config8(hda, 0x42, 0, 1 << 7 | 1 << 6); |
| 561 | log_debug("HDA disabled, I/O buffers routed to ADSP\n"); |
| 562 | |
| 563 | return 0; |
| 564 | } |
| 565 | |
Simon Glass | e7d04d8 | 2016-03-11 22:07:19 -0700 | [diff] [blame] | 566 | static int broadwell_pch_init(struct udevice *dev) |
| 567 | { |
| 568 | int ret; |
| 569 | |
| 570 | /* Enable upper 128 bytes of CMOS */ |
| 571 | setbits_le32(RCB_REG(RC), 1 << 2); |
| 572 | |
| 573 | /* |
| 574 | * TODO: TCO timer halt - this hangs |
| 575 | * setio_16(ACPI_BASE_ADDRESS + TCO1_CNT, TCO_TMR_HLT); |
| 576 | */ |
| 577 | |
| 578 | /* Disable unused device (always) */ |
| 579 | setbits_le32(RCB_REG(FD), PCH_DISABLE_ALWAYS); |
| 580 | |
| 581 | pch_misc_init(dev); |
| 582 | |
| 583 | /* Interrupt configuration */ |
| 584 | pch_enable_ioapic(); |
| 585 | |
| 586 | /* Initialize power management */ |
| 587 | ret = pch_power_options(dev); |
| 588 | if (ret) |
| 589 | return ret; |
| 590 | pch_pm_init(dev); |
| 591 | pch_cg_init(dev); |
Simon Glass | 3642ba9 | 2019-02-16 20:25:03 -0700 | [diff] [blame] | 592 | ret = pch_serialio_init(); |
| 593 | if (ret) |
| 594 | return ret; |
Simon Glass | e7d04d8 | 2016-03-11 22:07:19 -0700 | [diff] [blame] | 595 | systemagent_init(); |
| 596 | |
| 597 | return 0; |
| 598 | } |
| 599 | |
| 600 | static int broadwell_pch_probe(struct udevice *dev) |
| 601 | { |
| 602 | if (!(gd->flags & GD_FLG_RELOC)) |
| 603 | return broadwell_pch_early_init(dev); |
| 604 | else |
| 605 | return broadwell_pch_init(dev); |
| 606 | } |
| 607 | |
| 608 | static int broadwell_pch_get_spi_base(struct udevice *dev, ulong *sbasep) |
| 609 | { |
| 610 | u32 rcba; |
| 611 | |
| 612 | dm_pci_read_config32(dev, PCH_RCBA, &rcba); |
| 613 | /* Bits 31-14 are the base address, 13-1 are reserved, 0 is enable */ |
| 614 | rcba = rcba & 0xffffc000; |
| 615 | *sbasep = rcba + 0x3800; |
| 616 | |
| 617 | return 0; |
| 618 | } |
| 619 | |
| 620 | static int broadwell_set_spi_protect(struct udevice *dev, bool protect) |
| 621 | { |
| 622 | return lpc_set_spi_protect(dev, BIOS_CTRL, protect); |
| 623 | } |
| 624 | |
| 625 | static int broadwell_get_gpio_base(struct udevice *dev, u32 *gbasep) |
| 626 | { |
| 627 | dm_pci_read_config32(dev, GPIO_BASE, gbasep); |
| 628 | *gbasep &= PCI_BASE_ADDRESS_IO_MASK; |
| 629 | |
| 630 | return 0; |
| 631 | } |
| 632 | |
| 633 | static const struct pch_ops broadwell_pch_ops = { |
| 634 | .get_spi_base = broadwell_pch_get_spi_base, |
| 635 | .set_spi_protect = broadwell_set_spi_protect, |
| 636 | .get_gpio_base = broadwell_get_gpio_base, |
| 637 | }; |
| 638 | |
| 639 | static const struct udevice_id broadwell_pch_ids[] = { |
| 640 | { .compatible = "intel,broadwell-pch" }, |
| 641 | { } |
| 642 | }; |
| 643 | |
| 644 | U_BOOT_DRIVER(broadwell_pch) = { |
| 645 | .name = "broadwell_pch", |
| 646 | .id = UCLASS_PCH, |
| 647 | .of_match = broadwell_pch_ids, |
| 648 | .probe = broadwell_pch_probe, |
| 649 | .ops = &broadwell_pch_ops, |
| 650 | }; |