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git01.mediatek.com / filogic / uboot / 2ad80eeb38c690f3a537f47edd469ee7e8f7eae9 / . / configs / firefly-rk3399_defconfig
blob: 61f05b784fff06d0c6024b632ade9673e9d950f4 [file] [log] [blame]
Kever Yang6d43fb12017-04-24 11:58:30 +0800[diff] [blame]1CONFIG_ARM=y
2CONFIG_ARCH_ROCKCHIP=y
Tom Rini07edfae2018-02-03 12:10:38 -0500[diff] [blame]3CONFIG_SYS_TEXT_BASE=0x00200000
Kever Yang6d43fb12017-04-24 11:58:30 +0800[diff] [blame]4CONFIG_SPL_LIBCOMMON_SUPPORT=y
5CONFIG_SPL_LIBGENERIC_SUPPORT=y
6CONFIG_SYS_MALLOC_F_LEN=0x4000
7CONFIG_ROCKCHIP_RK3399=y
Kever Yangb5aba0d2018-11-09 11:21:38 +0800[diff] [blame]8CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x50000
Tom Rinic9285bf2019-04-29 15:54:04 -0400[diff] [blame]9CONFIG_NR_DRAM_BANKS=1
10CONFIG_SPL_STACK_R_ADDR=0x80000
Tom Rinie0056d72018-06-04 11:57:37 -0400[diff] [blame]11CONFIG_DEBUG_UART_BASE=0xFF1A0000
12CONFIG_DEBUG_UART_CLOCK=24000000
Tom Rini256aa742017-06-19 09:47:40 -0400[diff] [blame]13CONFIG_DEBUG_UART=y
Klaus Goger2b6b4f22018-05-25 23:45:05 +0200[diff] [blame]14CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-firefly.dtb"
Kever Yang6d43fb12017-04-24 11:58:30 +0800[diff] [blame]15# CONFIG_DISPLAY_CPUINFO is not set
Mario Sixf7055442018-03-28 14:38:17 +0200[diff] [blame]16CONFIG_DISPLAY_BOARDINFO_LATE=y
Kever Yang6d43fb12017-04-24 11:58:30 +0800[diff] [blame]17CONFIG_SPL_STACK_R=y
Kever Yangb5aba0d2018-11-09 11:21:38 +0800[diff] [blame]18CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
Kever Yangb5aba0d2018-11-09 11:21:38 +0800[diff] [blame]19CONFIG_TPL=y
Kever Yang6d43fb12017-04-24 11:58:30 +0800[diff] [blame]20CONFIG_CMD_BOOTZ=y
Kever Yang6d43fb12017-04-24 11:58:30 +0800[diff] [blame]21CONFIG_CMD_GPT=y
22CONFIG_CMD_MMC=y
23CONFIG_CMD_SF=y
24CONFIG_CMD_USB=y
25# CONFIG_CMD_SETEXPR is not set
26CONFIG_CMD_TIME=y
27CONFIG_SPL_OF_CONTROL=y
Tom Rini74060322018-09-03 15:26:12 -0400[diff] [blame]28CONFIG_DEFAULT_DEVICE_TREE="rk3399-firefly"
Kever Yang6d43fb12017-04-24 11:58:30 +0800[diff] [blame]29CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
Tom Rini5b0b0402017-08-28 07:16:32 -0400[diff] [blame]30CONFIG_ENV_IS_IN_MMC=y
Kever Yang6d43fb12017-04-24 11:58:30 +0800[diff] [blame]31CONFIG_ROCKCHIP_GPIO=y
32CONFIG_SYS_I2C_ROCKCHIP=y
33CONFIG_MMC_DW=y
Kever Yangd4335fc2017-06-14 16:31:48 +0800[diff] [blame]34CONFIG_MMC_DW_ROCKCHIP=y
Kever Yang6d43fb12017-04-24 11:58:30 +0800[diff] [blame]35CONFIG_MMC_SDHCI=y
36CONFIG_MMC_SDHCI_ROCKCHIP=y
Patrick Delaunay0df81042019-02-27 15:20:36 +0100[diff] [blame]37CONFIG_SF_DEFAULT_SPEED=20000000
Kever Yang6d43fb12017-04-24 11:58:30 +0800[diff] [blame]38CONFIG_DM_ETH=y
39CONFIG_ETH_DESIGNWARE=y
40CONFIG_GMAC_ROCKCHIP=y
Jacob Chen614704b2017-05-02 14:54:52 +0800[diff] [blame]41CONFIG_PMIC_RK8XX=y
Kever Yang6d43fb12017-04-24 11:58:30 +0800[diff] [blame]42CONFIG_REGULATOR_PWM=y
Jacob Chen614704b2017-05-02 14:54:52 +0800[diff] [blame]43CONFIG_REGULATOR_RK8XX=y
Kever Yang6d43fb12017-04-24 11:58:30 +0800[diff] [blame]44CONFIG_PWM_ROCKCHIP=y
Kever Yang6d43fb12017-04-24 11:58:30 +0800[diff] [blame]45CONFIG_BAUDRATE=1500000
Kever Yang6d43fb12017-04-24 11:58:30 +0800[diff] [blame]46CONFIG_DEBUG_UART_SHIFT=2
Kever Yang6d43fb12017-04-24 11:58:30 +0800[diff] [blame]47CONFIG_SYSRESET=y
48CONFIG_USB=y
49CONFIG_USB_XHCI_HCD=y
50CONFIG_USB_XHCI_DWC3=y
51CONFIG_USB_EHCI_HCD=y
52CONFIG_USB_EHCI_GENERIC=y
Chris Packham547cf412017-08-28 20:50:45 +1200[diff] [blame]53CONFIG_USB_HOST_ETHER=y
Chris Packhamb110e112017-08-28 20:50:46 +1200[diff] [blame]54CONFIG_USB_ETHER_ASIX=y
55CONFIG_USB_ETHER_ASIX88179=y
56CONFIG_USB_ETHER_MCS7830=y
57CONFIG_USB_ETHER_RTL8152=y
58CONFIG_USB_ETHER_SMSC95XX=y
Kever Yang6d43fb12017-04-24 11:58:30 +0800[diff] [blame]59CONFIG_USE_TINY_PRINTF=y
Kever Yangb5aba0d2018-11-09 11:21:38 +0800[diff] [blame]60CONFIG_SPL_TINY_MEMSET=y
Kever Yang6d43fb12017-04-24 11:58:30 +0800[diff] [blame]61CONFIG_ERRNO_STR=y