blob: eca78f8104a6f025db51887935be07fa48cd46f5 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Bo Shenc56e9f42015-03-27 14:23:34 +08002/*
3 * Copyright (C) 2015 Atmel Corporation
4 * Bo Shen <voice.shen@atmel.com>
Bo Shenc56e9f42015-03-27 14:23:34 +08005 */
6
7MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE, \
8 LENGTH = CONFIG_SPL_MAX_SIZE }
9MEMORY { .sdram : ORIGIN = CONFIG_SPL_BSS_START_ADDR, \
10 LENGTH = CONFIG_SPL_BSS_MAX_SIZE }
11
12OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
13OUTPUT_ARCH(arm)
14ENTRY(_start)
15SECTIONS
16{
17 .text :
18 {
19 __start = .;
20 *(.vectors)
21 arch/arm/cpu/arm926ejs/start.o (.text*)
22 *(.text*)
23 } >.sram
24
25 . = ALIGN(4);
26 .rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.sram
27
28 . = ALIGN(4);
29 .data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram
30
31 . = ALIGN(4);
Tom Rini0ed608e2016-03-15 17:56:29 -040032 .u_boot_list : { KEEP(*(SORT(.u_boot_list*))) } > .sram
33
34 . = ALIGN(4);
Bo Shenc56e9f42015-03-27 14:23:34 +080035 __image_copy_end = .;
36
37 .end :
38 {
39 *(.__end)
40 } >.sram
41
42 .bss :
43 {
44 . = ALIGN(4);
45 __bss_start = .;
46 *(.bss*)
47 . = ALIGN(4);
48 __bss_end = .;
49 } >.sdram
50}