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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Hans de Goedeb0d1ca22015-01-13 18:13:50 +01002/*
3 * (C) Copyright 2007-2011
4 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
5 * Tom Cubie <tangliang@allwinnertech.com>
Hans de Goedeb0d1ca22015-01-13 18:13:50 +01006 */
7
8#ifndef _SUNXI_CPU_SUN4I_H
9#define _SUNXI_CPU_SUN4I_H
10
11#define SUNXI_SRAM_A1_BASE 0x00000000
12#define SUNXI_SRAM_A1_SIZE (16 * 1024) /* 16 kiB */
13
Samuel Holland2a9c2382021-04-18 22:21:41 -050014#if defined(CONFIG_SUNXI_GEN_SUN6I) && \
15 !defined(CONFIG_MACH_SUN8I_R40) && \
16 !defined(CONFIG_MACH_SUN8I_V3S)
17#define SUNXI_SRAM_A2_BASE 0x00040000
18#ifdef CONFIG_MACH_SUN8I_H3
19#define SUNXI_SRAM_A2_SIZE (48 * 1024) /* 16+32 kiB */
20#else
21#define SUNXI_SRAM_A2_SIZE (80 * 1024) /* 16+64 kiB */
22#endif
23#else
Hans de Goedeb0d1ca22015-01-13 18:13:50 +010024#define SUNXI_SRAM_A2_BASE 0x00004000 /* 16 kiB */
Samuel Holland2a9c2382021-04-18 22:21:41 -050025#endif
Hans de Goedeb0d1ca22015-01-13 18:13:50 +010026#define SUNXI_SRAM_A3_BASE 0x00008000 /* 13 kiB */
27#define SUNXI_SRAM_A4_BASE 0x0000b400 /* 3 kiB */
28#define SUNXI_SRAM_D_BASE 0x00010000 /* 4 kiB */
29#define SUNXI_SRAM_B_BASE 0x00020000 /* 64 kiB (secure) */
30
Jernej Skrabec8d91b462017-03-27 19:22:32 +020031#define SUNXI_DE2_BASE 0x01000000
32
Chen-Yu Tsai8ba79742016-06-07 10:54:28 +080033#ifdef CONFIG_MACH_SUN8I_A83T
34#define SUNXI_CPUCFG_BASE 0x01700000
35#endif
36
Hans de Goedeb0d1ca22015-01-13 18:13:50 +010037#define SUNXI_SRAMC_BASE 0x01c00000
38#define SUNXI_DRAMC_BASE 0x01c01000
39#define SUNXI_DMA_BASE 0x01c02000
40#define SUNXI_NFC_BASE 0x01c03000
41#define SUNXI_TS_BASE 0x01c04000
42#define SUNXI_SPI0_BASE 0x01c05000
43#define SUNXI_SPI1_BASE 0x01c06000
44#define SUNXI_MS_BASE 0x01c07000
45#define SUNXI_TVD_BASE 0x01c08000
46#define SUNXI_CSI0_BASE 0x01c09000
Jernej Skrabeca3540822017-05-19 17:41:15 +020047#ifndef CONFIG_MACH_SUNXI_H3_H5
Hans de Goedeb0d1ca22015-01-13 18:13:50 +010048#define SUNXI_TVE0_BASE 0x01c0a000
Jernej Skrabeca3540822017-05-19 17:41:15 +020049#endif
Hans de Goedeb0d1ca22015-01-13 18:13:50 +010050#define SUNXI_EMAC_BASE 0x01c0b000
51#define SUNXI_LCD0_BASE 0x01c0C000
52#define SUNXI_LCD1_BASE 0x01c0d000
53#define SUNXI_VE_BASE 0x01c0e000
54#define SUNXI_MMC0_BASE 0x01c0f000
55#define SUNXI_MMC1_BASE 0x01c10000
56#define SUNXI_MMC2_BASE 0x01c11000
57#define SUNXI_MMC3_BASE 0x01c12000
Hans de Goedef07872b2015-04-06 20:33:34 +020058#ifdef CONFIG_SUNXI_GEN_SUN4I
Hans de Goedeb0d1ca22015-01-13 18:13:50 +010059#define SUNXI_USB0_BASE 0x01c13000
60#define SUNXI_USB1_BASE 0x01c14000
61#endif
62#define SUNXI_SS_BASE 0x01c15000
Jernej Skrabec8d91b462017-03-27 19:22:32 +020063#if !defined(CONFIG_MACH_SUNXI_H3_H5) && !defined(CONFIG_MACH_SUN50I)
Hans de Goedeb0d1ca22015-01-13 18:13:50 +010064#define SUNXI_HDMI_BASE 0x01c16000
Jernej Skrabec8d91b462017-03-27 19:22:32 +020065#endif
Hans de Goedeb0d1ca22015-01-13 18:13:50 +010066#define SUNXI_SPI2_BASE 0x01c17000
67#define SUNXI_SATA_BASE 0x01c18000
Hans de Goedef07872b2015-04-06 20:33:34 +020068#ifdef CONFIG_SUNXI_GEN_SUN4I
Hans de Goedeb0d1ca22015-01-13 18:13:50 +010069#define SUNXI_PATA_BASE 0x01c19000
70#define SUNXI_ACE_BASE 0x01c1a000
71#define SUNXI_TVE1_BASE 0x01c1b000
72#define SUNXI_USB2_BASE 0x01c1c000
Hans de Goedef07872b2015-04-06 20:33:34 +020073#endif
74#ifdef CONFIG_SUNXI_GEN_SUN6I
Andre Przywara5fb97432017-02-16 01:20:27 +000075#if defined(CONFIG_MACH_SUNXI_H3_H5) || defined(CONFIG_MACH_SUN50I)
Jelle van der Waaa1f5d112016-02-09 23:59:33 +010076#define SUNXI_USBPHY_BASE 0x01c19000
Jagan Teki179703342018-06-28 19:40:46 +053077#define SUNXI_USB0_BASE SUNXI_USBPHY_BASE
78#define SUNXI_USB1_BASE 0x01c1a000
79#define SUNXI_USB2_BASE 0x01c1b000
80#define SUNXI_USB3_BASE 0x01c1c000
81#define SUNXI_USB4_BASE 0x01c1d000
Jelle van der Waaa1f5d112016-02-09 23:59:33 +010082#else
Hans de Goedeb0d1ca22015-01-13 18:13:50 +010083#define SUNXI_USB0_BASE 0x01c19000
84#define SUNXI_USB1_BASE 0x01c1a000
85#define SUNXI_USB2_BASE 0x01c1b000
86#endif
Jelle van der Waaa1f5d112016-02-09 23:59:33 +010087#endif
Hans de Goedeb0d1ca22015-01-13 18:13:50 +010088#define SUNXI_CSI1_BASE 0x01c1d000
89#define SUNXI_TZASC_BASE 0x01c1e000
90#define SUNXI_SPI3_BASE 0x01c1f000
91
92#define SUNXI_CCM_BASE 0x01c20000
93#define SUNXI_INTC_BASE 0x01c20400
94#define SUNXI_PIO_BASE 0x01c20800
95#define SUNXI_TIMER_BASE 0x01c20c00
Hans de Goede663ae652016-08-19 15:25:41 +020096#ifndef CONFIG_SUNXI_GEN_SUN6I
97#define SUNXI_PWM_BASE 0x01c20e00
98#endif
Hans de Goedeb0d1ca22015-01-13 18:13:50 +010099#define SUNXI_SPDIF_BASE 0x01c21000
Hans de Goede663ae652016-08-19 15:25:41 +0200100#ifdef CONFIG_SUNXI_GEN_SUN6I
101#define SUNXI_PWM_BASE 0x01c21400
102#else
Hans de Goedeb0d1ca22015-01-13 18:13:50 +0100103#define SUNXI_AC97_BASE 0x01c21400
Hans de Goede663ae652016-08-19 15:25:41 +0200104#endif
Hans de Goedeb0d1ca22015-01-13 18:13:50 +0100105#define SUNXI_IR0_BASE 0x01c21800
106#define SUNXI_IR1_BASE 0x01c21c00
107
108#define SUNXI_IIS_BASE 0x01c22400
109#define SUNXI_LRADC_BASE 0x01c22800
110#define SUNXI_AD_DA_BASE 0x01c22c00
111#define SUNXI_KEYPAD_BASE 0x01c23000
112#define SUNXI_TZPC_BASE 0x01c23400
Chen-Yu Tsai7d7b6852016-01-27 16:34:43 +0800113
Andre Przywara5fb97432017-02-16 01:20:27 +0000114#if defined(CONFIG_MACH_SUN8I_A83T) || defined(CONFIG_MACH_SUNXI_H3_H5) || \
Amit Singh Tomard194c0e2016-07-06 17:59:44 +0530115defined(CONFIG_MACH_SUN50I)
Chen-Yu Tsai7d7b6852016-01-27 16:34:43 +0800116/* SID address space starts at 0x01c1400, but e-fuse is at offset 0x200 */
Icenowy Zheng1c40fed2016-12-20 02:03:36 +0800117#define SUNXI_SIDC_BASE 0x01c14000
Chen-Yu Tsai7d7b6852016-01-27 16:34:43 +0800118#define SUNXI_SID_BASE 0x01c14200
119#else
Hans de Goedeb0d1ca22015-01-13 18:13:50 +0100120#define SUNXI_SID_BASE 0x01c23800
Chen-Yu Tsai7d7b6852016-01-27 16:34:43 +0800121#endif
122
Hans de Goedeb0d1ca22015-01-13 18:13:50 +0100123#define SUNXI_SJTAG_BASE 0x01c23c00
124
125#define SUNXI_TP_BASE 0x01c25000
126#define SUNXI_PMU_BASE 0x01c25400
Chen-Yu Tsai8ba79742016-06-07 10:54:28 +0800127
Chen-Yu Tsai167bff52017-03-01 13:52:09 +0800128#if defined CONFIG_MACH_SUN7I || defined CONFIG_MACH_SUN8I_R40
Chen-Yu Tsai8ba79742016-06-07 10:54:28 +0800129#define SUNXI_CPUCFG_BASE 0x01c25c00
130#endif
Hans de Goedeb0d1ca22015-01-13 18:13:50 +0100131
132#define SUNXI_UART0_BASE 0x01c28000
133#define SUNXI_UART1_BASE 0x01c28400
134#define SUNXI_UART2_BASE 0x01c28800
135#define SUNXI_UART3_BASE 0x01c28c00
136#define SUNXI_UART4_BASE 0x01c29000
137#define SUNXI_UART5_BASE 0x01c29400
138#define SUNXI_UART6_BASE 0x01c29800
139#define SUNXI_UART7_BASE 0x01c29c00
140#define SUNXI_PS2_0_BASE 0x01c2a000
141#define SUNXI_PS2_1_BASE 0x01c2a400
142
143#define SUNXI_TWI0_BASE 0x01c2ac00
144#define SUNXI_TWI1_BASE 0x01c2b000
145#define SUNXI_TWI2_BASE 0x01c2b400
Paul Kocialkowski0a3ec0a2015-04-10 23:09:52 +0200146#ifdef CONFIG_MACH_SUN6I
147#define SUNXI_TWI3_BASE 0x01c0b800
148#endif
149#ifdef CONFIG_MACH_SUN7I
150#define SUNXI_TWI3_BASE 0x01c2b800
151#define SUNXI_TWI4_BASE 0x01c2c000
152#endif
Hans de Goedeb0d1ca22015-01-13 18:13:50 +0100153
154#define SUNXI_CAN_BASE 0x01c2bc00
155
156#define SUNXI_SCR_BASE 0x01c2c400
157
158#ifndef CONFIG_MACH_SUN6I
159#define SUNXI_GPS_BASE 0x01c30000
160#define SUNXI_MALI400_BASE 0x01c40000
161#define SUNXI_GMAC_BASE 0x01c50000
162#else
163#define SUNXI_GMAC_BASE 0x01c30000
164#endif
165
166#define SUNXI_DRAM_COM_BASE 0x01c62000
167#define SUNXI_DRAM_CTL0_BASE 0x01c63000
168#define SUNXI_DRAM_CTL1_BASE 0x01c64000
169#define SUNXI_DRAM_PHY0_BASE 0x01c65000
170#define SUNXI_DRAM_PHY1_BASE 0x01c66000
171
Chen-Yu Tsai9bffa7f2016-06-07 10:54:33 +0800172#define SUNXI_GIC400_BASE 0x01c80000
173
Hans de Goedeb0d1ca22015-01-13 18:13:50 +0100174/* module sram */
175#define SUNXI_SRAM_C_BASE 0x01d00000
176
Jernej Skrabeca3540822017-05-19 17:41:15 +0200177#ifndef CONFIG_MACH_SUN8I_H3
Hans de Goedeb0d1ca22015-01-13 18:13:50 +0100178#define SUNXI_DE_FE0_BASE 0x01e00000
Jernej Skrabeca3540822017-05-19 17:41:15 +0200179#else
180#define SUNXI_TVE0_BASE 0x01e00000
181#endif
Hans de Goedeb0d1ca22015-01-13 18:13:50 +0100182#define SUNXI_DE_FE1_BASE 0x01e20000
183#define SUNXI_DE_BE0_BASE 0x01e60000
Jernej Skrabeca3540822017-05-19 17:41:15 +0200184#ifndef CONFIG_MACH_SUN50I_H5
Hans de Goedeb0d1ca22015-01-13 18:13:50 +0100185#define SUNXI_DE_BE1_BASE 0x01e40000
Jernej Skrabeca3540822017-05-19 17:41:15 +0200186#else
187#define SUNXI_TVE0_BASE 0x01e40000
188#endif
Hans de Goedeb0d1ca22015-01-13 18:13:50 +0100189#define SUNXI_MP_BASE 0x01e80000
190#define SUNXI_AVG_BASE 0x01ea0000
191
Jernej Skrabec8d91b462017-03-27 19:22:32 +0200192#if defined(CONFIG_MACH_SUNXI_H3_H5) || defined(CONFIG_MACH_SUN50I)
193#define SUNXI_HDMI_BASE 0x01ee0000
194#endif
195
Hans de Goedeb0d1ca22015-01-13 18:13:50 +0100196#define SUNXI_RTC_BASE 0x01f00000
197#define SUNXI_PRCM_BASE 0x01f01400
Chen-Yu Tsai8ba79742016-06-07 10:54:28 +0800198
Chen-Yu Tsai167bff52017-03-01 13:52:09 +0800199#if defined CONFIG_SUNXI_GEN_SUN6I && \
200 !defined CONFIG_MACH_SUN8I_A83T && \
201 !defined CONFIG_MACH_SUN8I_R40
Chen-Yu Tsai8ba79742016-06-07 10:54:28 +0800202#define SUNXI_CPUCFG_BASE 0x01f01c00
203#endif
204
Jelle van der Waa8d3d7c12016-01-14 14:06:26 +0100205#define SUNXI_R_TWI_BASE 0x01f02400
Hans de Goedeb0d1ca22015-01-13 18:13:50 +0100206#define SUNXI_R_UART_BASE 0x01f02800
207#define SUNXI_R_PIO_BASE 0x01f02c00
208#define SUN6I_P2WI_BASE 0x01f03400
209#define SUNXI_RSB_BASE 0x01f03400
210
211/* CoreSight Debug Module */
212#define SUNXI_CSDM_BASE 0x3f500000
213
214#define SUNXI_DDRII_DDRIII_BASE 0x40000000 /* 2 GiB */
215
216#define SUNXI_BROM_BASE 0xffff0000 /* 32 kiB */
217
218#define SUNXI_CPU_CFG (SUNXI_TIMER_BASE + 0x13c)
219
220/* SS bonding ids used for cpu identification */
221#define SUNXI_SS_BOND_ID_A31 4
222#define SUNXI_SS_BOND_ID_A31S 5
223
224#ifndef __ASSEMBLY__
225void sunxi_board_init(void);
226void sunxi_reset(void);
227int sunxi_get_ss_bonding_id(void);
228int sunxi_get_sid(unsigned int *sid);
229#endif /* __ASSEMBLY__ */
230
231#endif /* _SUNXI_CPU_SUN4I_H */