| wdenk | d9fce81 | 2003-06-28 17:24:46 +0000 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2003 |
| 3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
| 4 | * |
| 5 | * See file CREDITS for list of people who contributed to this |
| 6 | * project. |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or |
| 9 | * modify it under the terms of the GNU General Public License as |
| 10 | * published by the Free Software Foundation; either version 2 of |
| 11 | * the License, or (at your option) any later version. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | * GNU General Public License for more details. |
| 17 | * |
| 18 | * You should have received a copy of the GNU General Public License |
| 19 | * along with this program; if not, write to the Free Software |
| 20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 21 | * MA 02111-1307 USA |
| 22 | */ |
| 23 | |
| 24 | #define GPIO_CPU_LED GPIO_3 |
| 25 | |
| 26 | |
| 27 | #define CPLD_BASE 0x10000000 /* t.b.m. */ |
| Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 28 | #define DEBUG_LEDS_ADDR CPLD_BASE + 0x01 |
| 29 | #define HW_ID_ADDR CPLD_BASE + 0x02 |
| 30 | #define DIP_SWITCH_ADDR CPLD_BASE + 0x04 |
| 31 | #define PHY_CTRL_ADDR CPLD_BASE + 0x05 |
| 32 | #define SPI_OUT_ADDR CPLD_BASE + 0x07 |
| 33 | #define SPI_IN_ADDR CPLD_BASE + 0x08 |
| 34 | #define MDIO_OUT_ADDR CPLD_BASE + 0x09 |
| 35 | #define MDIO_IN_ADDR CPLD_BASE + 0x0A |
| 36 | #define MISC_OUT_ADDR CPLD_BASE + 0x0B |
| wdenk | d9fce81 | 2003-06-28 17:24:46 +0000 | [diff] [blame] | 37 | |
| 38 | /* Addresses used on I2C bus */ |
| 39 | #define LM75_CHIP_ADDR 0x9C |
| 40 | #define LM75_CPU_ADDR 0x9E |
| 41 | #define SDRAM_SPD_ADDR 0xA0 |
| 42 | |
| 43 | #define SDRAM_SPD_WRITE_ADDRESS (SDRAM_SPD_ADDR) |
| 44 | #define SDRAM_SPD_READ_ADDRESS (SDRAM_SPD_ADDR+1) |
| 45 | |
| 46 | #ifndef FALSE |
| 47 | #define FALSE 0 |
| 48 | #endif |
| 49 | |
| 50 | #ifndef TRUE |
| 51 | #define TRUE 1 |
| 52 | #endif |