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git01.mediatek.com / filogic / uboot / 2a61b442c9dc34bc9c60f840aadf7cf42fd2a00f / . / drivers / ddr / marvell / a38x / ddr3_init.h
blob: e2ff040b001c8a4acdd8199fc840cac4f1472e3b [file] [log] [blame]
Stefan Roese5ffceb82015-03-26 15:36:56 +0100[diff] [blame]1/*
2 * Copyright (C) Marvell International Ltd. and its affiliates
3 *
4 * SPDX-License-Identifier: GPL-2.0
5 */
6
7#ifndef _DDR3_INIT_H
8#define _DDR3_INIT_H
9
10#if defined(CONFIG_ARMADA_38X)
11#include "ddr3_a38x.h"
12#include "ddr3_a38x_mc_static.h"
13#include "ddr3_a38x_topology.h"
14#endif
15#include "ddr3_hws_hw_training.h"
16#include "ddr3_hws_sil_training.h"
17#include "ddr3_logging_def.h"
18#include "ddr3_training_hw_algo.h"
19#include "ddr3_training_ip.h"
20#include "ddr3_training_ip_centralization.h"
21#include "ddr3_training_ip_engine.h"
22#include "ddr3_training_ip_flow.h"
23#include "ddr3_training_ip_pbs.h"
24#include "ddr3_training_ip_prv_if.h"
25#include "ddr3_training_ip_static.h"
26#include "ddr3_training_leveling.h"
27#include "xor.h"
28
29/*
30 * MV_DEBUG_INIT need to be defines, otherwise the output of the
31 * DDR2 training code is not complete and misleading
32 */
33#define MV_DEBUG_INIT
34
35#define BIT(x) (1 << (x))
36
37#ifdef MV_DEBUG_INIT
38#define DEBUG_INIT_S(s) puts(s)
39#define DEBUG_INIT_D(d, l) printf("%x", d)
40#define DEBUG_INIT_D_10(d, l) printf("%d", d)
41#else
42#define DEBUG_INIT_S(s)
43#define DEBUG_INIT_D(d, l)
44#define DEBUG_INIT_D_10(d, l)
45#endif
46
47#ifdef MV_DEBUG_INIT_FULL
48#define DEBUG_INIT_FULL_S(s) puts(s)
49#define DEBUG_INIT_FULL_D(d, l) printf("%x", d)
50#define DEBUG_INIT_FULL_D_10(d, l) printf("%d", d)
51#define DEBUG_WR_REG(reg, val) \
52 { DEBUG_INIT_S("Write Reg: 0x"); DEBUG_INIT_D((reg), 8); \
53 DEBUG_INIT_S("= "); DEBUG_INIT_D((val), 8); DEBUG_INIT_S("\n"); }
54#define DEBUG_RD_REG(reg, val) \
55 { DEBUG_INIT_S("Read Reg: 0x"); DEBUG_INIT_D((reg), 8); \
56 DEBUG_INIT_S("= "); DEBUG_INIT_D((val), 8); DEBUG_INIT_S("\n"); }
57#else
58#define DEBUG_INIT_FULL_S(s)
59#define DEBUG_INIT_FULL_D(d, l)
60#define DEBUG_INIT_FULL_D_10(d, l)
61#define DEBUG_WR_REG(reg, val)
62#define DEBUG_RD_REG(reg, val)
63#endif
64
65#define DEBUG_INIT_FULL_C(s, d, l) \
66 { DEBUG_INIT_FULL_S(s); \
67 DEBUG_INIT_FULL_D(d, l); \
68 DEBUG_INIT_FULL_S("\n"); }
69#define DEBUG_INIT_C(s, d, l) \
70 { DEBUG_INIT_S(s); DEBUG_INIT_D(d, l); DEBUG_INIT_S("\n"); }
71
72/*
73 * Debug (Enable/Disable modules) and Error report
74 */
75
76#ifdef BASIC_DEBUG
77#define MV_DEBUG_WL
78#define MV_DEBUG_RL
79#define MV_DEBUG_DQS_RESULTS
80#endif
81
82#ifdef FULL_DEBUG
83#define MV_DEBUG_WL
84#define MV_DEBUG_RL
85#define MV_DEBUG_DQS
86
87#define MV_DEBUG_PBS
88#define MV_DEBUG_DFS
89#define MV_DEBUG_MAIN_FULL
90#define MV_DEBUG_DFS_FULL
91#define MV_DEBUG_DQS_FULL
92#define MV_DEBUG_RL_FULL
93#define MV_DEBUG_WL_FULL
94#endif
95
96#if defined(CONFIG_ARMADA_38X)
97#include "ddr3_a38x.h"
98#include "ddr3_a38x_topology.h"
99#endif
100
101/* The following is a list of Marvell status */
102#define MV_ERROR (-1)
103#define MV_OK (0x00) /* Operation succeeded */
104#define MV_FAIL (0x01) /* Operation failed */
105#define MV_BAD_VALUE (0x02) /* Illegal value (general) */
106#define MV_OUT_OF_RANGE (0x03) /* The value is out of range */
107#define MV_BAD_PARAM (0x04) /* Illegal parameter in function called */
108#define MV_BAD_PTR (0x05) /* Illegal pointer value */
109#define MV_BAD_SIZE (0x06) /* Illegal size */
110#define MV_BAD_STATE (0x07) /* Illegal state of state machine */
111#define MV_SET_ERROR (0x08) /* Set operation failed */
112#define MV_GET_ERROR (0x09) /* Get operation failed */
113#define MV_CREATE_ERROR (0x0a) /* Fail while creating an item */
114#define MV_NOT_FOUND (0x0b) /* Item not found */
115#define MV_NO_MORE (0x0c) /* No more items found */
116#define MV_NO_SUCH (0x0d) /* No such item */
117#define MV_TIMEOUT (0x0e) /* Time Out */
118#define MV_NO_CHANGE (0x0f) /* Parameter(s) is already in this value */
119#define MV_NOT_SUPPORTED (0x10) /* This request is not support */
120#define MV_NOT_IMPLEMENTED (0x11) /* Request supported but not implemented*/
121#define MV_NOT_INITIALIZED (0x12) /* The item is not initialized */
122#define MV_NO_RESOURCE (0x13) /* Resource not available (memory ...) */
123#define MV_FULL (0x14) /* Item is full (Queue or table etc...) */
124#define MV_EMPTY (0x15) /* Item is empty (Queue or table etc...) */
125#define MV_INIT_ERROR (0x16) /* Error occured while INIT process */
126#define MV_HW_ERROR (0x17) /* Hardware error */
127#define MV_TX_ERROR (0x18) /* Transmit operation not succeeded */
128#define MV_RX_ERROR (0x19) /* Recieve operation not succeeded */
129#define MV_NOT_READY (0x1a) /* The other side is not ready yet */
130#define MV_ALREADY_EXIST (0x1b) /* Tried to create existing item */
131#define MV_OUT_OF_CPU_MEM (0x1c) /* Cpu memory allocation failed. */
132#define MV_NOT_STARTED (0x1d) /* Not started yet */
133#define MV_BUSY (0x1e) /* Item is busy. */
134#define MV_TERMINATE (0x1f) /* Item terminates it's work. */
135#define MV_NOT_ALIGNED (0x20) /* Wrong alignment */
136#define MV_NOT_ALLOWED (0x21) /* Operation NOT allowed */
137#define MV_WRITE_PROTECT (0x22) /* Write protected */
138#define MV_INVALID (int)(-1)
139
140/* For checking function return values */
141#define CHECK_STATUS(orig_func) \
142 { \
143 int status; \
144 status = orig_func; \
145 if (MV_OK != status) \
146 return status; \
147 }
148
149enum log_level {
150 MV_LOG_LEVEL_0,
151 MV_LOG_LEVEL_1,
152 MV_LOG_LEVEL_2,
153 MV_LOG_LEVEL_3
154};
155
156/* Globals */
157extern u8 debug_training;
158extern u8 is_reg_dump;
159extern u8 generic_init_controller;
160extern u32 freq_val[];
161extern u32 is_pll_old;
162extern struct cl_val_per_freq cas_latency_table[];
163extern struct pattern_info pattern_table[];
164extern struct cl_val_per_freq cas_write_latency_table[];
165extern u8 debug_training;
166extern u8 debug_centralization, debug_training_ip, debug_training_bist,
167 debug_pbs, debug_training_static, debug_leveling;
168extern u32 pipe_multicast_mask;
169extern struct hws_tip_config_func_db config_func_info[];
170extern u8 cs_mask_reg[];
171extern u8 twr_mask_table[];
172extern u8 cl_mask_table[];
173extern u8 cwl_mask_table[];
174extern u16 rfc_table[];
175extern u32 speed_bin_table_t_rc[];
176extern u32 speed_bin_table_t_rcd_t_rp[];
177extern u32 ck_delay, ck_delay_16;
178
179extern u32 g_zpri_data;
180extern u32 g_znri_data;
181extern u32 g_zpri_ctrl;
182extern u32 g_znri_ctrl;
183extern u32 g_zpodt_data;
184extern u32 g_znodt_data;
185extern u32 g_zpodt_ctrl;
186extern u32 g_znodt_ctrl;
187extern u32 g_dic;
188extern u32 g_odt_config;
189extern u32 g_rtt_nom;
190
191extern u8 debug_training_access;
192extern u8 debug_training_a38x;
193extern u32 first_active_if;
194extern enum hws_ddr_freq init_freq;
195extern u32 delay_enable, ck_delay, ck_delay_16, ca_delay;
196extern u32 mask_tune_func;
197extern u32 rl_version;
198extern int rl_mid_freq_wa;
199extern u8 calibration_update_control; /* 2 external only, 1 is internal only */
200extern enum hws_ddr_freq medium_freq;
201
202extern u32 ck_delay, ck_delay_16;
203extern enum hws_result training_result[MAX_STAGE_LIMIT][MAX_INTERFACE_NUM];
204extern u32 first_active_if;
205extern u32 mask_tune_func;
206extern u32 freq_val[];
207extern enum hws_ddr_freq init_freq;
208extern enum hws_ddr_freq low_freq;
209extern enum hws_ddr_freq medium_freq;
210extern u8 generic_init_controller;
211extern enum auto_tune_stage training_stage;
212extern u32 is_pll_before_init;
213extern u32 is_adll_calib_before_init;
214extern u32 is_dfs_in_init;
215extern int wl_debug_delay;
216extern u32 silicon_delay[HWS_MAX_DEVICE_NUM];
217extern u32 p_finger;
218extern u32 n_finger;
219extern u32 freq_val[DDR_FREQ_LIMIT];
220extern u32 start_pattern, end_pattern;
221extern u32 phy_reg0_val;
222extern u32 phy_reg1_val;
223extern u32 phy_reg2_val;
224extern u32 phy_reg3_val;
225extern enum hws_pattern sweep_pattern;
226extern enum hws_pattern pbs_pattern;
227extern u8 is_rzq6;
228extern u32 znri_data_phy_val;
229extern u32 zpri_data_phy_val;
230extern u32 znri_ctrl_phy_val;
231extern u32 zpri_ctrl_phy_val;
232extern u8 debug_training_access;
233extern u32 finger_test, p_finger_start, p_finger_end, n_finger_start,
234 n_finger_end, p_finger_step, n_finger_step;
235extern u32 mode2_t;
236extern u32 xsb_validate_type;
237extern u32 xsb_validation_base_address;
238extern u32 odt_additional;
239extern u32 debug_mode;
240extern u32 delay_enable;
241extern u32 ca_delay;
242extern u32 debug_dunit;
243extern u32 clamp_tbl[];
244extern u32 freq_mask[HWS_MAX_DEVICE_NUM][DDR_FREQ_LIMIT];
245extern u32 start_pattern, end_pattern;
246
247extern u32 maxt_poll_tries;
248extern u32 is_bist_reset_bit;
249extern u8 debug_training_bist;
250
251extern u8 vref_window_size[MAX_INTERFACE_NUM][MAX_BUS_NUM];
252extern u32 debug_mode;
253extern u32 effective_cs;
254extern int ddr3_tip_centr_skip_min_win_check;
255extern u32 *dq_map_table;
256extern enum auto_tune_stage training_stage;
257extern u8 debug_centralization;
258
259extern u32 delay_enable;
260extern u32 start_pattern, end_pattern;
261extern u32 freq_val[DDR_FREQ_LIMIT];
262extern u8 debug_training_hw_alg;
263extern enum auto_tune_stage training_stage;
264
265extern u8 debug_training_ip;
266extern enum hws_result training_result[MAX_STAGE_LIMIT][MAX_INTERFACE_NUM];
267extern enum auto_tune_stage training_stage;
268extern u32 effective_cs;
269
270extern u8 debug_leveling;
271extern enum hws_result training_result[MAX_STAGE_LIMIT][MAX_INTERFACE_NUM];
272extern enum auto_tune_stage training_stage;
273extern u32 rl_version;
274extern struct cl_val_per_freq cas_latency_table[];
275extern u32 start_xsb_offset;
276extern u32 debug_mode;
277extern u32 odt_config;
278extern u32 effective_cs;
279extern u32 phy_reg1_val;
280
281extern u8 debug_pbs;
282extern u32 effective_cs;
283extern u16 mask_results_dq_reg_map[];
284extern enum hws_ddr_freq medium_freq;
285extern u32 freq_val[];
286extern enum hws_result training_result[MAX_STAGE_LIMIT][MAX_INTERFACE_NUM];
287extern enum auto_tune_stage training_stage;
288extern u32 debug_mode;
289extern u32 *dq_map_table;
290
291extern u32 vref;
292extern struct cl_val_per_freq cas_latency_table[];
293extern u32 target_freq;
294extern struct hws_tip_config_func_db config_func_info[HWS_MAX_DEVICE_NUM];
295extern u32 clamp_tbl[];
296extern u32 init_freq;
297/* list of allowed frequency listed in order of enum hws_ddr_freq */
298extern u32 freq_val[];
299extern u8 debug_training_static;
300extern u32 first_active_if;
301
302/* Prototypes */
303int ddr3_tip_enable_init_sequence(u32 dev_num);
304
305int ddr3_tip_init_a38x(u32 dev_num, u32 board_id);
306
307int ddr3_hws_hw_training(void);
308int ddr3_silicon_pre_init(void);
309int ddr3_silicon_post_init(void);
310int ddr3_post_run_alg(void);
311int ddr3_if_ecc_enabled(void);
312void ddr3_new_tip_ecc_scrub(void);
313
314void ddr3_print_version(void);
315void ddr3_new_tip_dlb_config(void);
316struct hws_topology_map *ddr3_get_topology_map(void);
317
318int ddr3_if_ecc_enabled(void);
319int ddr3_tip_reg_write(u32 dev_num, u32 reg_addr, u32 data);
320int ddr3_tip_reg_read(u32 dev_num, u32 reg_addr, u32 *data, u32 reg_mask);
321int ddr3_silicon_get_ddr_target_freq(u32 *ddr_freq);
322int ddr3_tip_a38x_get_freq_config(u8 dev_num, enum hws_ddr_freq freq,
323 struct hws_tip_freq_config_info
324 *freq_config_info);
325int ddr3_a38x_update_topology_map(u32 dev_num,
326 struct hws_topology_map *topology_map);
327int ddr3_tip_a38x_get_init_freq(int dev_num, enum hws_ddr_freq *freq);
328int ddr3_tip_a38x_get_medium_freq(int dev_num, enum hws_ddr_freq *freq);
329int ddr3_tip_a38x_if_read(u8 dev_num, enum hws_access_type interface_access,
330 u32 if_id, u32 reg_addr, u32 *data, u32 mask);
331int ddr3_tip_a38x_if_write(u8 dev_num, enum hws_access_type interface_access,
332 u32 if_id, u32 reg_addr, u32 data, u32 mask);
333int ddr3_tip_a38x_get_device_info(u8 dev_num,
334 struct ddr3_device_info *info_ptr);
335
336int ddr3_tip_init_a38x(u32 dev_num, u32 board_id);
337
338int print_adll(u32 dev_num, u32 adll[MAX_INTERFACE_NUM * MAX_BUS_NUM]);
339int ddr3_tip_restore_dunit_regs(u32 dev_num);
340void print_topology(struct hws_topology_map *topology_db);
341
342u32 mv_board_id_get(void);
343
344int ddr3_load_topology_map(void);
345int ddr3_tip_init_specific_reg_config(u32 dev_num,
346 struct reg_data *reg_config_arr);
347u32 ddr3_tip_get_init_freq(void);
348void ddr3_hws_set_log_level(enum ddr_lib_debug_block block, u8 level);
349int ddr3_tip_tune_training_params(u32 dev_num,
350 struct tune_train_params *params);
351void get_target_freq(u32 freq_mode, u32 *ddr_freq, u32 *hclk_ps);
352int ddr3_fast_path_dynamic_cs_size_config(u32 cs_ena);
353void ddr3_fast_path_static_cs_size_config(u32 cs_ena);
354u32 ddr3_get_device_width(u32 cs);
355u32 mv_board_id_index_get(u32 board_id);
356u32 mv_board_id_get(void);
357u32 ddr3_get_bus_width(void);
358void ddr3_set_log_level(u32 n_log_level);
359int ddr3_calc_mem_cs_size(u32 cs, u32 *cs_size);
360
361int hws_ddr3_cs_base_adr_calc(u32 if_id, u32 cs, u32 *cs_base_addr);
362
363int ddr3_tip_print_pbs_result(u32 dev_num, u32 cs_num, enum pbs_dir pbs_mode);
364int ddr3_tip_clean_pbs_result(u32 dev_num, enum pbs_dir pbs_mode);
365
366int ddr3_tip_static_round_trip_arr_build(u32 dev_num,
367 struct trip_delay_element *table_ptr,
368 int is_wl, u32 *round_trip_delay_arr);
369
370u32 hws_ddr3_tip_max_cs_get(void);
371
372/*
373 * Accessor functions for the registers
374 */
375static inline void reg_write(u32 addr, u32 val)
376{
377 writel(val, INTER_REGS_BASE + addr);
378}
379
380static inline u32 reg_read(u32 addr)
381{
382 return readl(INTER_REGS_BASE + addr);
383}
384
385static inline void reg_bit_set(u32 addr, u32 mask)
386{
387 setbits_le32(INTER_REGS_BASE + addr, mask);
388}
389
390static inline void reg_bit_clr(u32 addr, u32 mask)
391{
392 clrbits_le32(INTER_REGS_BASE + addr, mask);
393}
394
395#endif /* _DDR3_INIT_H */