Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
TsiChung Liew | 0ee47d4 | 2010-03-11 22:12:53 -0600 | [diff] [blame] | 2 | /* |
| 3 | * ColdFire cache |
| 4 | * |
Alison Wang | fdc2fb1 | 2012-10-18 19:25:51 +0000 | [diff] [blame] | 5 | * Copyright 2004-2012 Freescale Semiconductor, Inc. |
TsiChung Liew | 0ee47d4 | 2010-03-11 22:12:53 -0600 | [diff] [blame] | 6 | * TsiChung Liew (Tsi-Chung.Liew@freescale.com) |
TsiChung Liew | 0ee47d4 | 2010-03-11 22:12:53 -0600 | [diff] [blame] | 7 | */ |
| 8 | |
| 9 | #ifndef __CACHE_H |
| 10 | #define __CACHE_H |
| 11 | |
Tom Rini | 2a526c3 | 2023-12-14 13:16:51 -0500 | [diff] [blame^] | 12 | #include <config.h> |
| 13 | |
TsiChung Liew | 0ee47d4 | 2010-03-11 22:12:53 -0600 | [diff] [blame] | 14 | #if defined(CONFIG_MCF520x) || defined(CONFIG_MCF523x) || \ |
Tom Rini | 1cd175e | 2021-07-12 12:42:14 -0400 | [diff] [blame] | 15 | defined(CONFIG_MCF52x2) |
Tom Rini | 364d002 | 2023-01-10 11:19:45 -0500 | [diff] [blame] | 16 | #define CFG_CF_V2 |
TsiChung Liew | 0ee47d4 | 2010-03-11 22:12:53 -0600 | [diff] [blame] | 17 | #endif |
| 18 | |
angelo@sysam.it | bb4ba2c | 2015-02-12 01:40:00 +0100 | [diff] [blame] | 19 | #if defined(CONFIG_MCF530x) || defined(CONFIG_MCF532x) || \ |
| 20 | defined(CONFIG_MCF5301x) |
Tom Rini | 364d002 | 2023-01-10 11:19:45 -0500 | [diff] [blame] | 21 | #define CFG_CF_V3 |
TsiChung Liew | 0ee47d4 | 2010-03-11 22:12:53 -0600 | [diff] [blame] | 22 | #endif |
| 23 | |
Tom Rini | 3d59ab7 | 2021-07-12 12:42:13 -0400 | [diff] [blame] | 24 | #if defined(CONFIG_MCF5441x) |
Tom Rini | 364d002 | 2023-01-10 11:19:45 -0500 | [diff] [blame] | 25 | #define CFG_CF_V4E /* Four Extra ACRn */ |
TsiChung Liew | 0ee47d4 | 2010-03-11 22:12:53 -0600 | [diff] [blame] | 26 | #endif |
TsiChung Liew | 0ee47d4 | 2010-03-11 22:12:53 -0600 | [diff] [blame] | 27 | |
| 28 | /* ***** CACR ***** */ |
| 29 | /* V2 Core */ |
Tom Rini | 364d002 | 2023-01-10 11:19:45 -0500 | [diff] [blame] | 30 | #ifdef CFG_CF_V2 |
TsiChung Liew | 0ee47d4 | 2010-03-11 22:12:53 -0600 | [diff] [blame] | 31 | |
| 32 | #define CF_CACR_CENB (1 << 31) |
| 33 | #define CF_CACR_CPD (1 << 28) |
| 34 | #define CF_CACR_CFRZ (1 << 27) |
| 35 | #define CF_CACR_CEIB (1 << 10) |
| 36 | #define CF_CACR_DCM (1 << 9) |
| 37 | #define CF_CACR_DBWE (1 << 8) |
| 38 | |
| 39 | #if defined(CONFIG_MCF5249) || defined(CONFIG_MCF5253) |
| 40 | #define CF_CACR_DWP (1 << 6) |
| 41 | #else |
| 42 | #define CF_CACR_CINV (1 << 24) |
| 43 | #define CF_CACR_DISI (1 << 23) |
| 44 | #define CF_CACR_DISD (1 << 22) |
| 45 | #define CF_CACR_INVI (1 << 21) |
| 46 | #define CF_CACR_INVD (1 << 20) |
| 47 | #define CF_CACR_DWP (1 << 5) |
| 48 | #define CF_CACR_EUSP (1 << 4) |
| 49 | #endif /* CONFIG_MCF5249 || CONFIG_MCF5253 */ |
| 50 | |
Tom Rini | 364d002 | 2023-01-10 11:19:45 -0500 | [diff] [blame] | 51 | #endif /* CFG_CF_V2 */ |
TsiChung Liew | 0ee47d4 | 2010-03-11 22:12:53 -0600 | [diff] [blame] | 52 | |
| 53 | /* V3 Core */ |
Tom Rini | 364d002 | 2023-01-10 11:19:45 -0500 | [diff] [blame] | 54 | #ifdef CFG_CF_V3 |
TsiChung Liew | 0ee47d4 | 2010-03-11 22:12:53 -0600 | [diff] [blame] | 55 | |
| 56 | #define CF_CACR_EC (1 << 31) |
| 57 | #define CF_CACR_ESB (1 << 29) |
| 58 | #define CF_CACR_DPI (1 << 28) |
| 59 | #define CF_CACR_HLCK (1 << 27) |
| 60 | #define CF_CACR_CINVA (1 << 24) |
| 61 | #define CF_CACR_DNFB (1 << 10) |
| 62 | #define CF_CACR_DCM_UNMASK 0xFFFFFCFF |
| 63 | #define CF_CACR_DCM_WT (0 << 8) |
| 64 | #define CF_CACR_DCM_CB (1 << 8) |
| 65 | #define CF_CACR_DCM_P (2 << 8) |
| 66 | #define CF_CACR_DCM_IP (3 << 8) |
| 67 | #define CF_CACR_DW (1 << 5) |
| 68 | #define CF_CACR_EUSP (1 << 4) |
| 69 | |
Tom Rini | 364d002 | 2023-01-10 11:19:45 -0500 | [diff] [blame] | 70 | #endif /* CFG_CF_V3 */ |
TsiChung Liew | 0ee47d4 | 2010-03-11 22:12:53 -0600 | [diff] [blame] | 71 | |
| 72 | /* V4 Core */ |
Tom Rini | 364d002 | 2023-01-10 11:19:45 -0500 | [diff] [blame] | 73 | #if defined(CONFIG_CF_V4) || defined(CFG_CF_V4E) |
TsiChung Liew | 0ee47d4 | 2010-03-11 22:12:53 -0600 | [diff] [blame] | 74 | |
| 75 | #define CF_CACR_DEC (1 << 31) |
| 76 | #define CF_CACR_DW (1 << 30) |
| 77 | #define CF_CACR_DESB (1 << 29) |
| 78 | #define CF_CACR_DDPI (1 << 28) |
| 79 | #define CF_CACR_DHLCK (1 << 27) |
| 80 | #define CF_CACR_DDCM_UNMASK (0xF9FFFFFF) |
| 81 | #define CF_CACR_DDCM_WT (0 << 25) |
| 82 | #define CF_CACR_DDCM_CB (1 << 25) |
| 83 | #define CF_CACR_DDCM_P (2 << 25) |
| 84 | #define CF_CACR_DDCM_IP (3 << 25) |
| 85 | #define CF_CACR_DCINVA (1 << 24) |
| 86 | |
| 87 | #define CF_CACR_DDSP (1 << 23) |
| 88 | #define CF_CACR_BEC (1 << 19) |
| 89 | #define CF_CACR_BCINVA (1 << 18) |
| 90 | #define CF_CACR_IEC (1 << 15) |
| 91 | #define CF_CACR_DNFB (1 << 13) |
| 92 | #define CF_CACR_IDPI (1 << 12) |
| 93 | #define CF_CACR_IHLCK (1 << 11) |
| 94 | #define CF_CACR_IDCM (1 << 10) |
| 95 | #define CF_CACR_ICINVA (1 << 8) |
| 96 | #define CF_CACR_IDSP (1 << 7) |
| 97 | #define CF_CACR_EUSP (1 << 5) |
| 98 | |
Alison Wang | fdc2fb1 | 2012-10-18 19:25:51 +0000 | [diff] [blame] | 99 | #if defined(CONFIG_MCF5445x) || defined(CONFIG_MCF5441x) |
TsiChung Liew | 0ee47d4 | 2010-03-11 22:12:53 -0600 | [diff] [blame] | 100 | #define CF_CACR_IVO (1 << 20) |
| 101 | #define CF_CACR_SPA (1 << 14) |
| 102 | #else |
| 103 | #define CF_CACR_DF (1 << 4) |
| 104 | #endif |
| 105 | |
| 106 | #endif /* CONFIG_CF_V4 */ |
| 107 | |
| 108 | /* ***** ACR ***** */ |
| 109 | #define CF_ACR_ADR_UNMASK (0x00FFFFFF) |
| 110 | #define CF_ACR_ADR(x) ((x & 0xFF) << 24) |
| 111 | #define CF_ACR_ADRMSK_UNMASK (0xFF00FFFF) |
| 112 | #define CF_ACR_ADRMSK(x) ((x & 0xFF) << 16) |
| 113 | #define CF_ACR_EN (1 << 15) |
| 114 | #define CF_ACR_SM_UNMASK (0xFFFF9FFF) |
| 115 | #define CF_ACR_SM_UM (0 << 13) |
| 116 | #define CF_ACR_SM_SM (1 << 13) |
| 117 | #define CF_ACR_SM_ALL (3 << 13) |
| 118 | #define CF_ACR_WP (1 << 2) |
| 119 | |
| 120 | /* V2 Core */ |
Tom Rini | 364d002 | 2023-01-10 11:19:45 -0500 | [diff] [blame] | 121 | #ifdef CFG_CF_V2 |
TsiChung Liew | 0ee47d4 | 2010-03-11 22:12:53 -0600 | [diff] [blame] | 122 | #define CF_ACR_CM (1 << 6) |
| 123 | #define CF_ACR_BWE (1 << 5) |
| 124 | #else |
| 125 | /* V3 & V4 */ |
| 126 | #define CF_ACR_CM_UNMASK (0xFFFFFF9F) |
| 127 | #define CF_ACR_CM_WT (0 << 5) |
| 128 | #define CF_ACR_CM_CB (1 << 5) |
| 129 | #define CF_ACR_CM_P (2 << 5) |
| 130 | #define CF_ACR_CM_IP (3 << 5) |
Tom Rini | 364d002 | 2023-01-10 11:19:45 -0500 | [diff] [blame] | 131 | #endif /* CFG_CF_V2 */ |
TsiChung Liew | 0ee47d4 | 2010-03-11 22:12:53 -0600 | [diff] [blame] | 132 | |
| 133 | /* V4 Core */ |
Tom Rini | 364d002 | 2023-01-10 11:19:45 -0500 | [diff] [blame] | 134 | #if defined(CONFIG_CF_V4) || defined(CFG_CF_V4E) |
TsiChung Liew | 0ee47d4 | 2010-03-11 22:12:53 -0600 | [diff] [blame] | 135 | #define CF_ACR_AMM (1 << 10) |
| 136 | #define CF_ACR_SP (1 << 3) |
| 137 | #endif /* CONFIG_CF_V4 */ |
| 138 | |
| 139 | |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 140 | #ifndef CFG_SYS_CACHE_ICACR |
| 141 | #define CFG_SYS_CACHE_ICACR 0 |
TsiChung Liew | 0ee47d4 | 2010-03-11 22:12:53 -0600 | [diff] [blame] | 142 | #endif |
| 143 | |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 144 | #ifndef CFG_SYS_CACHE_DCACR |
| 145 | #ifdef CFG_SYS_CACHE_ICACR |
| 146 | #define CFG_SYS_CACHE_DCACR CFG_SYS_CACHE_ICACR |
TsiChung Liew | 0ee47d4 | 2010-03-11 22:12:53 -0600 | [diff] [blame] | 147 | #else |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 148 | #define CFG_SYS_CACHE_DCACR 0 |
TsiChung Liew | 0ee47d4 | 2010-03-11 22:12:53 -0600 | [diff] [blame] | 149 | #endif |
| 150 | #endif |
| 151 | |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 152 | #ifndef CFG_SYS_CACHE_ACR0 |
| 153 | #define CFG_SYS_CACHE_ACR0 0 |
TsiChung Liew | 0ee47d4 | 2010-03-11 22:12:53 -0600 | [diff] [blame] | 154 | #endif |
| 155 | |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 156 | #ifndef CFG_SYS_CACHE_ACR1 |
| 157 | #define CFG_SYS_CACHE_ACR1 0 |
TsiChung Liew | 0ee47d4 | 2010-03-11 22:12:53 -0600 | [diff] [blame] | 158 | #endif |
| 159 | |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 160 | #ifndef CFG_SYS_CACHE_ACR2 |
| 161 | #define CFG_SYS_CACHE_ACR2 0 |
TsiChung Liew | 0ee47d4 | 2010-03-11 22:12:53 -0600 | [diff] [blame] | 162 | #endif |
| 163 | |
Tom Rini | 364d002 | 2023-01-10 11:19:45 -0500 | [diff] [blame] | 164 | #ifndef CFG_SYS_CACHE_ACR3 |
| 165 | #define CFG_SYS_CACHE_ACR3 0 |
TsiChung Liew | 0ee47d4 | 2010-03-11 22:12:53 -0600 | [diff] [blame] | 166 | #endif |
| 167 | |
Tom Rini | 364d002 | 2023-01-10 11:19:45 -0500 | [diff] [blame] | 168 | #ifndef CFG_SYS_CACHE_ACR4 |
| 169 | #define CFG_SYS_CACHE_ACR4 0 |
TsiChung Liew | 0ee47d4 | 2010-03-11 22:12:53 -0600 | [diff] [blame] | 170 | #endif |
| 171 | |
Tom Rini | 364d002 | 2023-01-10 11:19:45 -0500 | [diff] [blame] | 172 | #ifndef CFG_SYS_CACHE_ACR5 |
| 173 | #define CFG_SYS_CACHE_ACR5 0 |
TsiChung Liew | 0ee47d4 | 2010-03-11 22:12:53 -0600 | [diff] [blame] | 174 | #endif |
| 175 | |
Tom Rini | 364d002 | 2023-01-10 11:19:45 -0500 | [diff] [blame] | 176 | #ifndef CFG_SYS_CACHE_ACR6 |
| 177 | #define CFG_SYS_CACHE_ACR6 0 |
TsiChung Liew | 0ee47d4 | 2010-03-11 22:12:53 -0600 | [diff] [blame] | 178 | #endif |
| 179 | |
Tom Rini | 364d002 | 2023-01-10 11:19:45 -0500 | [diff] [blame] | 180 | #ifndef CFG_SYS_CACHE_ACR7 |
| 181 | #define CFG_SYS_CACHE_ACR7 0 |
TsiChung Liew | 0ee47d4 | 2010-03-11 22:12:53 -0600 | [diff] [blame] | 182 | #endif |
| 183 | |
| 184 | #define CF_ADDRMASK(x) (((x > 0x10) ? ((x >> 4) - 1) : (x)) << 16) |
| 185 | |
| 186 | #ifndef __ASSEMBLY__ /* put C only stuff in this section */ |
| 187 | |
| 188 | void icache_invalid(void); |
| 189 | void dcache_invalid(void); |
| 190 | |
| 191 | #endif |
| 192 | |
Anton Staaf | fe7d4f9 | 2011-10-17 16:46:04 -0700 | [diff] [blame] | 193 | /* |
| 194 | * m68k uses 16 byte L1 data cache line sizes. Use this for DMA buffer |
| 195 | * alignment unless the board configuration has specified a new value. |
| 196 | */ |
| 197 | #ifdef CONFIG_SYS_CACHELINE_SIZE |
| 198 | #define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE |
| 199 | #else |
| 200 | #define ARCH_DMA_MINALIGN 16 |
| 201 | #endif |
| 202 | |
TsiChung Liew | 0ee47d4 | 2010-03-11 22:12:53 -0600 | [diff] [blame] | 203 | #endif /* __CACHE_H */ |