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Alex Marginean72f3aa52021-01-27 13:00:00 +02001// SPDX-License-Identifier: GPL-2.0+ OR X11
2/*
3 * NXP LS1028A-QDS device tree fragment for RCW 9999
4 *
Vladimir Oltean5041e422021-09-17 14:27:13 +03005 * Copyright 2019-2021 NXP
Alex Marginean72f3aa52021-01-27 13:00:00 +02006 *
7 */
8
9/*
10 * This set-up is using SCH-24801 cards with VSC8234 quad SGMII PHY.
11 *
12 * Switch ports are mapped 1:1 to VSC8234 card ports seated in slot 1.
13 * Top port is port 0.
14 *
15 * The following DTS assumes DIP SW5[1-3] = 000b.
16 */
17
18&slot1 {
19 #include "fsl-sch-24801.dtsi"
20};
21
Michael Walle2a20ed12021-10-13 18:14:15 +020022&enetc_port2 {
Vladimir Olteanc32039a2021-06-29 20:53:11 +030023 status = "okay";
24};
25
Alex Marginean72f3aa52021-01-27 13:00:00 +020026&mscc_felix {
27 status = "okay";
28};
29
30&mscc_felix_port0 {
31 status = "okay";
32 phy-mode = "sgmii";
Michael Walle2da16cd2021-10-13 18:14:05 +020033 phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@1c}>;
Alex Marginean72f3aa52021-01-27 13:00:00 +020034};
35
36&mscc_felix_port1 {
37 status = "okay";
38 phy-mode = "sgmii";
Michael Walle2da16cd2021-10-13 18:14:05 +020039 phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@1d}>;
Alex Marginean72f3aa52021-01-27 13:00:00 +020040};
41
42&mscc_felix_port2 {
43 status = "okay";
44 phy-mode = "sgmii";
Michael Walle2da16cd2021-10-13 18:14:05 +020045 phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@1e}>;
Alex Marginean72f3aa52021-01-27 13:00:00 +020046};
47
48&mscc_felix_port3 {
49 status = "okay";
50 phy-mode = "sgmii";
Michael Walle2da16cd2021-10-13 18:14:05 +020051 phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@1f}>;
Alex Marginean72f3aa52021-01-27 13:00:00 +020052};
Vladimir Olteanc32039a2021-06-29 20:53:11 +030053
54&mscc_felix_port4 {
Michael Walle2a20ed12021-10-13 18:14:15 +020055 ethernet = <&enetc_port2>;
Vladimir Olteanc32039a2021-06-29 20:53:11 +030056 status = "okay";
57};