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git01.mediatek.com / filogic / uboot / 2a20ed13bdb107bc06168a501023b3dd4f018a70 / . / arch / arm / dts / fsl-ls1028a-kontron-sl28.dts
blob: 9ae70ba5416ee33b5eb1f06a1b51c41e5bf57375 [file] [log] [blame]
Michael Walle36ba7642020-10-15 23:08:57 +0200[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Device Tree file for the Kontron SMARC-sAL28 board.
4 *
5 * Copyright (C) 2019 Michael Walle <michael@walle.cc>
6 *
7 */
8
9/dts-v1/;
10#include "fsl-ls1028a.dtsi"
11
12/ {
13 model = "Kontron SMARC-sAL28";
14 compatible = "kontron,sl28", "fsl,ls1028a";
15
16 aliases {
Michael Walle2a20ed12021-10-13 18:14:15 +0200[diff] [blame^]17 serial0 = &duart0;
18 serial1 = &duart1;
Michael Walle36ba7642020-10-15 23:08:57 +0200[diff] [blame]19 serial2 = &lpuart1;
20 spi0 = &fspi;
21 spi1 = &dspi2;
22 };
23
24 chosen {
25 stdout-path = "serial0:115200n8";
26 };
27};
28
29&dspi2 {
30 status = "okay";
31};
32
Michael Walle2a20ed12021-10-13 18:14:15 +0200[diff] [blame^]33&enetc_port0 {
Michael Walle36ba7642020-10-15 23:08:57 +0200[diff] [blame]34 phy-handle = <&phy0>;
35 phy-mode = "sgmii";
36 status = "okay";
37};
38
Michael Walle2a20ed12021-10-13 18:14:15 +0200[diff] [blame^]39&enetc_port2 {
Michael Walle36ba7642020-10-15 23:08:57 +0200[diff] [blame]40 status = "disabled";
41};
42
Michael Walle2a20ed12021-10-13 18:14:15 +0200[diff] [blame^]43&enetc_port3 {
Michael Walle36ba7642020-10-15 23:08:57 +0200[diff] [blame]44 status = "disabled";
45};
46
Michael Walle2a20ed12021-10-13 18:14:15 +0200[diff] [blame^]47&esdhc {
Michael Walle36ba7642020-10-15 23:08:57 +0200[diff] [blame]48 sd-uhs-sdr104;
49 sd-uhs-sdr50;
50 sd-uhs-sdr25;
51 sd-uhs-sdr12;
52 status = "okay";
53};
54
55&esdhc1 {
56 mmc-hs200-1_8v;
57 mmc-hs400-1_8v;
58 bus-width = <8>;
59 status = "okay";
60};
61
62&fspi {
63 status = "okay";
64
65 flash@0 {
66 #address-cells = <1>;
67 #size-cells = <1>;
68 compatible = "jedec,spi-nor";
69 m25p,fast-read;
70 spi-max-frequency = <133000000>;
71 reg = <0>;
72 /* The following setting enables 1-1-2 (CMD-ADDR-DATA) mode */
73 spi-rx-bus-width = <2>; /* 2 SPI Rx lines */
74 spi-tx-bus-width = <1>; /* 1 SPI Tx line */
Michael Walle36ba7642020-10-15 23:08:57 +0200[diff] [blame]75 };
76};
77
78&i2c0 {
79 status = "okay";
80
81 rtc@32 {
82 compatible = "microcrystal,rv8803";
83 reg = <0x32>;
84 };
85
86 eeprom@50 {
87 compatible = "atmel,24c32";
88 reg = <0x50>;
89 pagesize = <32>;
90 };
91};
92
93&i2c3 {
94 status = "okay";
95};
96
97&i2c4 {
98 status = "okay";
99
100 eeprom@50 {
101 compatible = "atmel,24c32";
102 reg = <0x50>;
103 pagesize = <32>;
104 };
105};
106
107&lpuart1 {
108 status = "okay";
109};
110
Michael Walle2a20ed12021-10-13 18:14:15 +0200[diff] [blame^]111&enetc_mdio_pf3 {
Michael Walle36ba7642020-10-15 23:08:57 +0200[diff] [blame]112 status = "okay";
113 phy0: ethernet-phy@5 {
114 reg = <0x5>;
115 eee-broken-1000t;
116 eee-broken-100tx;
117 };
118};
119
Michael Walle101410e2021-01-08 00:08:59 +0100[diff] [blame]120&sata {
121 status = "okay";
122};
123
Michael Walle2a20ed12021-10-13 18:14:15 +0200[diff] [blame^]124&duart0 {
Michael Walle36ba7642020-10-15 23:08:57 +0200[diff] [blame]125 status = "okay";
126};
127
Michael Walle2a20ed12021-10-13 18:14:15 +0200[diff] [blame^]128&duart1 {
Michael Walle36ba7642020-10-15 23:08:57 +0200[diff] [blame]129 status = "okay";
130};
131
Michael Walle2a20ed12021-10-13 18:14:15 +0200[diff] [blame^]132&usb0 {
Michael Walle36ba7642020-10-15 23:08:57 +0200[diff] [blame]133 status = "okay";
134};
135
Michael Walle2a20ed12021-10-13 18:14:15 +0200[diff] [blame^]136&usb1 {
Michael Walle36ba7642020-10-15 23:08:57 +0200[diff] [blame]137 status = "okay";
138};