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git01.mediatek.com / filogic / uboot / 29e289cc46f4a066eca1753575b814f18731a9c0 / . / arch / arm / include / asm / arch-rockchip / ioc_rk3588.h
blob: 7ad98466c39a40eb703a594b5656eb0cffc5b31c [file] [log] [blame]
Jagan Teki5a03d1d2023-01-30 20:27:41 +0530[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * (C) Copyright 2021 Rockchip Electronics Co., Ltd.
4 */
5#ifndef _ASM_ARCH_IOC_RK3588_H
6#define _ASM_ARCH_IOC_RK3588_H
7
Quentin Schulz29e289c2024-03-11 13:01:55 +0100[diff] [blame^]8#define BUS_IOC_BASE 0xfd5f8000
9
Jagan Teki5a03d1d2023-01-30 20:27:41 +0530[diff] [blame]10struct rk3588_bus_ioc {
11 unsigned int reserved0000[3]; /* Address Offset: 0x0000 */
12 unsigned int gpio0b_iomux_sel_h; /* Address Offset: 0x000C */
13 unsigned int gpio0c_iomux_sel_l; /* Address Offset: 0x0010 */
14 unsigned int gpio0c_iomux_sel_h; /* Address Offset: 0x0014 */
15 unsigned int gpio0d_iomux_sel_l; /* Address Offset: 0x0018 */
16 unsigned int gpio0d_iomux_sel_h; /* Address Offset: 0x001C */
17 unsigned int gpio1a_iomux_sel_l; /* Address Offset: 0x0020 */
18 unsigned int gpio1a_iomux_sel_h; /* Address Offset: 0x0024 */
19 unsigned int gpio1b_iomux_sel_l; /* Address Offset: 0x0028 */
20 unsigned int gpio1b_iomux_sel_h; /* Address Offset: 0x002C */
21 unsigned int gpio1c_iomux_sel_l; /* Address Offset: 0x0030 */
22 unsigned int gpio1c_iomux_sel_h; /* Address Offset: 0x0034 */
23 unsigned int gpio1d_iomux_sel_l; /* Address Offset: 0x0038 */
24 unsigned int gpio1d_iomux_sel_h; /* Address Offset: 0x003C */
25 unsigned int gpio2a_iomux_sel_l; /* Address Offset: 0x0040 */
26 unsigned int gpio2a_iomux_sel_h; /* Address Offset: 0x0044 */
27 unsigned int gpio2b_iomux_sel_l; /* Address Offset: 0x0048 */
28 unsigned int gpio2b_iomux_sel_h; /* Address Offset: 0x004C */
29 unsigned int gpio2c_iomux_sel_l; /* Address Offset: 0x0050 */
30 unsigned int gpio2c_iomux_sel_h; /* Address Offset: 0x0054 */
31 unsigned int gpio2d_iomux_sel_l; /* Address Offset: 0x0058 */
32 unsigned int gpio2d_iomux_sel_h; /* Address Offset: 0x005C */
33 unsigned int gpio3a_iomux_sel_l; /* Address Offset: 0x0060 */
34 unsigned int gpio3a_iomux_sel_h; /* Address Offset: 0x0064 */
35 unsigned int gpio3b_iomux_sel_l; /* Address Offset: 0x0068 */
36 unsigned int gpio3b_iomux_sel_h; /* Address Offset: 0x006C */
37 unsigned int gpio3c_iomux_sel_l; /* Address Offset: 0x0070 */
38 unsigned int gpio3c_iomux_sel_h; /* Address Offset: 0x0074 */
39 unsigned int gpio3d_iomux_sel_l; /* Address Offset: 0x0078 */
40 unsigned int gpio3d_iomux_sel_h; /* Address Offset: 0x007C */
41 unsigned int gpio4a_iomux_sel_l; /* Address Offset: 0x0080 */
42 unsigned int gpio4a_iomux_sel_h; /* Address Offset: 0x0084 */
43 unsigned int gpio4b_iomux_sel_l; /* Address Offset: 0x0088 */
44 unsigned int gpio4b_iomux_sel_h; /* Address Offset: 0x008C */
45 unsigned int gpio4c_iomux_sel_l; /* Address Offset: 0x0090 */
46 unsigned int gpio4c_iomux_sel_h; /* Address Offset: 0x0094 */
47 unsigned int gpio4d_iomux_sel_l; /* Address Offset: 0x0098 */
48 unsigned int gpio4d_iomux_sel_h; /* Address Offset: 0x009C */
49};
50
51check_member(rk3588_bus_ioc, gpio4d_iomux_sel_h, 0x009C);
52
Quentin Schulz29e289c2024-03-11 13:01:55 +0100[diff] [blame^]53#define PMU1_IOC_BASE 0xfd5f0000
54
Jagan Teki5a03d1d2023-01-30 20:27:41 +0530[diff] [blame]55struct rk3588_pmu1_ioc {
56 unsigned int gpio0a_iomux_sel_l; /* Address Offset: 0x0000 */
57 unsigned int gpio0a_iomux_sel_h; /* Address Offset: 0x0004 */
58 unsigned int gpio0b_iomux_sel_l; /* Address Offset: 0x0008 */
59 unsigned int reserved0012; /* Address Offset: 0x000C */
60 unsigned int gpio0a_ds_l; /* Address Offset: 0x0010 */
61 unsigned int gpio0a_ds_h; /* Address Offset: 0x0014 */
62 unsigned int gpio0b_ds_l; /* Address Offset: 0x0018 */
63 unsigned int reserved0028; /* Address Offset: 0x001C */
64 unsigned int gpio0a_p; /* Address Offset: 0x0020 */
65 unsigned int gpio0b_p; /* Address Offset: 0x0024 */
66 unsigned int gpio0a_ie; /* Address Offset: 0x0028 */
67 unsigned int gpio0b_ie; /* Address Offset: 0x002C */
68 unsigned int gpio0a_smt; /* Address Offset: 0x0030 */
69 unsigned int gpio0b_smt; /* Address Offset: 0x0034 */
70 unsigned int gpio0a_pdis; /* Address Offset: 0x0038 */
71 unsigned int gpio0b_pdis; /* Address Offset: 0x003C */
72 unsigned int xin_con; /* Address Offset: 0x0040 */
73};
74
75check_member(rk3588_pmu1_ioc, xin_con, 0x0040);
76
Quentin Schulz29e289c2024-03-11 13:01:55 +0100[diff] [blame^]77#define PMU2_IOC_BASE 0xfd5f4000
78
Jagan Teki5a03d1d2023-01-30 20:27:41 +0530[diff] [blame]79struct rk3588_pmu2_ioc {
80 unsigned int gpio0b_iomux_sel_h; /* Address Offset: 0x0000 */
81 unsigned int gpio0c_iomux_sel_l; /* Address Offset: 0x0004 */
82 unsigned int gpio0c_iomux_sel_h; /* Address Offset: 0x0008 */
83 unsigned int gpio0d_iomux_sel_l; /* Address Offset: 0x000C */
84 unsigned int gpio0d_iomux_sel_h; /* Address Offset: 0x0010 */
85 unsigned int gpio0b_ds_h; /* Address Offset: 0x0014 */
86 unsigned int gpio0c_ds_l; /* Address Offset: 0x0018 */
87 unsigned int gpio0c_ds_h; /* Address Offset: 0x001C */
88 unsigned int gpio0d_ds_l; /* Address Offset: 0x0020 */
89 unsigned int gpio0d_ds_h; /* Address Offset: 0x0024 */
90 unsigned int gpio0b_p; /* Address Offset: 0x0028 */
91 unsigned int gpio0c_p; /* Address Offset: 0x002C */
92 unsigned int gpio0d_p; /* Address Offset: 0x0030 */
93 unsigned int gpio0b_ie; /* Address Offset: 0x0034 */
94 unsigned int gpio0c_ie; /* Address Offset: 0x0038 */
95 unsigned int gpio0d_ie; /* Address Offset: 0x003C */
96 unsigned int gpio0b_smt; /* Address Offset: 0x0040 */
97 unsigned int gpio0c_smt; /* Address Offset: 0x0044 */
98 unsigned int gpio0d_smt; /* Address Offset: 0x0048 */
99 unsigned int gpio0b_pdis; /* Address Offset: 0x004C */
100 unsigned int gpio0c_pdis; /* Address Offset: 0x0050 */
101 unsigned int gpio0d_pdis; /* Address Offset: 0x0054 */
102};
103
104check_member(rk3588_pmu2_ioc, gpio0d_pdis, 0x0054);
105
106#endif
107