developer | 29d9d9f | 2025-01-10 16:41:13 +0800 | [diff] [blame^] | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
| 2 | /* |
| 3 | * Copyright (C) 2025 MediaTek Inc. |
| 4 | * |
| 5 | * Author: Weijie Gao <weijie.gao@mediatek.com> |
| 6 | * Author: Mark Lee <mark-mc.lee@mediatek.com> |
| 7 | */ |
| 8 | |
| 9 | #ifndef _MTK_ETH_H_ |
| 10 | #define _MTK_ETH_H_ |
| 11 | |
| 12 | #include <linker_lists.h> |
| 13 | #include <linux/bitops.h> |
| 14 | #include <linux/bitfield.h> |
| 15 | |
| 16 | struct mtk_eth_priv; |
| 17 | struct mtk_eth_switch_priv; |
| 18 | |
| 19 | /* struct mtk_soc_data - This is the structure holding all differences |
| 20 | * among various plaforms |
| 21 | * @caps Flags shown the extra capability for the SoC |
| 22 | * @ana_rgc3: The offset for register ANA_RGC3 related to |
| 23 | * sgmiisys syscon |
| 24 | * @gdma_count: Number of GDMAs |
| 25 | * @pdma_base: Register base of PDMA block |
| 26 | * @txd_size: Tx DMA descriptor size. |
| 27 | * @rxd_size: Rx DMA descriptor size. |
| 28 | */ |
| 29 | struct mtk_soc_data { |
| 30 | u32 caps; |
| 31 | u32 ana_rgc3; |
| 32 | u32 gdma_count; |
| 33 | u32 pdma_base; |
| 34 | u32 txd_size; |
| 35 | u32 rxd_size; |
| 36 | }; |
| 37 | |
| 38 | struct mtk_eth_switch { |
| 39 | const char *name; |
| 40 | const char *desc; |
| 41 | size_t priv_size; |
| 42 | u32 reset_wait_time; |
| 43 | |
| 44 | int (*detect)(struct mtk_eth_priv *priv); |
| 45 | int (*setup)(struct mtk_eth_switch_priv *priv); |
| 46 | int (*cleanup)(struct mtk_eth_switch_priv *priv); |
| 47 | void (*mac_control)(struct mtk_eth_switch_priv *priv, bool enable); |
| 48 | }; |
| 49 | |
| 50 | #define MTK_ETH_SWITCH(__name) \ |
| 51 | ll_entry_declare(struct mtk_eth_switch, __name, mtk_eth_switch) |
| 52 | |
| 53 | struct mtk_eth_switch_priv { |
| 54 | struct mtk_eth_priv *eth; |
| 55 | const struct mtk_eth_switch *sw; |
| 56 | const struct mtk_soc_data *soc; |
| 57 | void *ethsys_base; |
| 58 | int phy_interface; |
| 59 | }; |
| 60 | |
| 61 | enum mkt_eth_capabilities { |
| 62 | MTK_TRGMII_BIT, |
| 63 | MTK_TRGMII_MT7621_CLK_BIT, |
| 64 | MTK_U3_COPHY_V2_BIT, |
| 65 | MTK_INFRA_BIT, |
| 66 | MTK_NETSYS_V2_BIT, |
| 67 | MTK_NETSYS_V3_BIT, |
| 68 | |
| 69 | /* PATH BITS */ |
| 70 | MTK_ETH_PATH_GMAC1_TRGMII_BIT, |
| 71 | MTK_ETH_PATH_GMAC2_SGMII_BIT, |
| 72 | MTK_ETH_PATH_MT7622_SGMII_BIT, |
| 73 | MTK_ETH_PATH_MT7629_GMAC2_BIT, |
| 74 | }; |
| 75 | |
| 76 | #define MTK_TRGMII BIT(MTK_TRGMII_BIT) |
| 77 | #define MTK_TRGMII_MT7621_CLK BIT(MTK_TRGMII_MT7621_CLK_BIT) |
| 78 | #define MTK_U3_COPHY_V2 BIT(MTK_U3_COPHY_V2_BIT) |
| 79 | #define MTK_INFRA BIT(MTK_INFRA_BIT) |
| 80 | #define MTK_NETSYS_V2 BIT(MTK_NETSYS_V2_BIT) |
| 81 | #define MTK_NETSYS_V3 BIT(MTK_NETSYS_V3_BIT) |
| 82 | |
| 83 | /* Supported path present on SoCs */ |
| 84 | #define MTK_ETH_PATH_GMAC1_TRGMII BIT(MTK_ETH_PATH_GMAC1_TRGMII_BIT) |
| 85 | #define MTK_ETH_PATH_GMAC2_SGMII BIT(MTK_ETH_PATH_GMAC2_SGMII_BIT) |
| 86 | #define MTK_ETH_PATH_MT7622_SGMII BIT(MTK_ETH_PATH_MT7622_SGMII_BIT) |
| 87 | #define MTK_ETH_PATH_MT7629_GMAC2 BIT(MTK_ETH_PATH_MT7629_GMAC2_BIT) |
| 88 | |
| 89 | #define MTK_GMAC1_TRGMII (MTK_ETH_PATH_GMAC1_TRGMII | MTK_TRGMII) |
| 90 | |
| 91 | #define MTK_GMAC2_U3_QPHY (MTK_ETH_PATH_GMAC2_SGMII | MTK_U3_COPHY_V2 | MTK_INFRA) |
| 92 | |
| 93 | #define MTK_HAS_CAPS(caps, _x) (((caps) & (_x)) == (_x)) |
| 94 | |
| 95 | #define MT7621_CAPS (MTK_GMAC1_TRGMII | MTK_TRGMII_MT7621_CLK) |
| 96 | |
| 97 | #define MT7622_CAPS (MTK_ETH_PATH_MT7622_SGMII) |
| 98 | |
| 99 | #define MT7623_CAPS (MTK_GMAC1_TRGMII) |
| 100 | |
| 101 | #define MT7629_CAPS (MTK_ETH_PATH_MT7629_GMAC2 | MTK_INFRA) |
| 102 | |
| 103 | #define MT7981_CAPS (MTK_GMAC2_U3_QPHY | MTK_NETSYS_V2) |
| 104 | |
| 105 | #define MT7986_CAPS (MTK_NETSYS_V2) |
| 106 | |
| 107 | #define MT7987_CAPS (MTK_NETSYS_V3 | MTK_GMAC2_U3_QPHY | MTK_INFRA) |
| 108 | |
| 109 | #define MT7988_CAPS (MTK_NETSYS_V3 | MTK_INFRA) |
| 110 | |
| 111 | /* Frame Engine Register Bases */ |
| 112 | #define PDMA_V1_BASE 0x0800 |
| 113 | #define PDMA_V2_BASE 0x6000 |
| 114 | #define PDMA_V3_BASE 0x6800 |
| 115 | #define GDMA1_BASE 0x0500 |
| 116 | #define GDMA2_BASE 0x1500 |
| 117 | #define GDMA3_BASE 0x0540 |
| 118 | #define GMAC_BASE 0x10000 |
| 119 | #define GSW_BASE 0x20000 |
| 120 | |
| 121 | /* Ethernet subsystem registers */ |
| 122 | #define ETHSYS_SYSCFG1_REG 0x14 |
| 123 | #define SYSCFG1_GE_MODE_S(n) (12 + ((n) * 2)) |
| 124 | #define SYSCFG1_GE_MODE_M 0x3 |
| 125 | #define SYSCFG1_SGMII_SEL_M GENMASK(9, 8) |
| 126 | #define SYSCFG1_SGMII_SEL(gmac) BIT(9 - (gmac)) |
| 127 | |
| 128 | #define ETHSYS_CLKCFG0_REG 0x2c |
| 129 | #define ETHSYS_TRGMII_CLK_SEL362_5 BIT(11) |
| 130 | |
| 131 | /* Top misc registers */ |
| 132 | #define TOPMISC_NETSYS_PCS_MUX 0x84 |
| 133 | #define NETSYS_PCS_MUX_MASK GENMASK(1, 0) |
| 134 | #define MUX_G2_USXGMII_SEL BIT(1) |
| 135 | #define MUX_HSGMII1_G1_SEL BIT(0) |
| 136 | |
| 137 | #define USB_PHY_SWITCH_REG 0x218 |
| 138 | #define QPHY_SEL_MASK 0x3 |
| 139 | #define SGMII_QPHY_SEL 0x2 |
| 140 | |
| 141 | #define MT7629_INFRA_MISC2_REG 0x70c |
| 142 | #define INFRA_MISC2_BONDING_OPTION GENMASK(15, 0) |
| 143 | |
| 144 | /* SYSCFG1_GE_MODE: GE Modes */ |
| 145 | #define GE_MODE_RGMII 0 |
| 146 | #define GE_MODE_MII 1 |
| 147 | #define GE_MODE_MII_PHY 2 |
| 148 | #define GE_MODE_RMII 3 |
| 149 | |
| 150 | /* SGMII subsystem config registers */ |
| 151 | #define SGMSYS_PCS_CONTROL_1 0x0 |
| 152 | #define SGMII_LINK_STATUS BIT(18) |
| 153 | #define SGMII_AN_ENABLE BIT(12) |
| 154 | #define SGMII_AN_RESTART BIT(9) |
| 155 | |
| 156 | #define SGMSYS_SGMII_MODE 0x20 |
| 157 | #define SGMII_AN_MODE 0x31120103 |
| 158 | #define SGMII_FORCE_MODE 0x31120019 |
| 159 | |
| 160 | #define SGMSYS_QPHY_PWR_STATE_CTRL 0xe8 |
| 161 | #define SGMII_PHYA_PWD BIT(4) |
| 162 | |
| 163 | #define SGMSYS_QPHY_WRAP_CTRL 0xec |
| 164 | #define SGMII_PN_SWAP_TX_RX 0x03 |
| 165 | |
| 166 | #define SGMSYS_GEN2_SPEED 0x2028 |
| 167 | #define SGMSYS_GEN2_SPEED_V2 0x128 |
| 168 | #define SGMSYS_SPEED_MASK GENMASK(3, 2) |
| 169 | #define SGMSYS_SPEED_2500 1 |
| 170 | |
| 171 | /* USXGMII subsystem config registers */ |
| 172 | /* Register to control USXGMII XFI PLL digital */ |
| 173 | #define XFI_PLL_DIG_GLB8 0x08 |
| 174 | #define RG_XFI_PLL_EN BIT(31) |
| 175 | |
| 176 | /* Register to control USXGMII XFI PLL analog */ |
| 177 | #define XFI_PLL_ANA_GLB8 0x108 |
| 178 | #define RG_XFI_PLL_ANA_SWWA 0x02283248 |
| 179 | |
| 180 | /* Frame Engine Registers */ |
| 181 | #define PSE_NO_DROP_CFG_REG 0x108 |
| 182 | #define PSE_NO_DROP_GDM1 BIT(1) |
| 183 | |
| 184 | #define FE_GLO_MISC_REG 0x124 |
| 185 | #define PDMA_VER_V2 BIT(4) |
| 186 | |
| 187 | /* PDMA */ |
| 188 | #define TX_BASE_PTR_REG(n) (0x000 + (n) * 0x10) |
| 189 | #define TX_MAX_CNT_REG(n) (0x004 + (n) * 0x10) |
| 190 | #define TX_CTX_IDX_REG(n) (0x008 + (n) * 0x10) |
| 191 | #define TX_DTX_IDX_REG(n) (0x00c + (n) * 0x10) |
| 192 | |
| 193 | #define RX_BASE_PTR_REG(n) (0x100 + (n) * 0x10) |
| 194 | #define RX_MAX_CNT_REG(n) (0x104 + (n) * 0x10) |
| 195 | #define RX_CRX_IDX_REG(n) (0x108 + (n) * 0x10) |
| 196 | #define RX_DRX_IDX_REG(n) (0x10c + (n) * 0x10) |
| 197 | |
| 198 | #define PDMA_GLO_CFG_REG 0x204 |
| 199 | #define TX_WB_DDONE BIT(6) |
| 200 | #define RX_DMA_BUSY BIT(3) |
| 201 | #define RX_DMA_EN BIT(2) |
| 202 | #define TX_DMA_BUSY BIT(1) |
| 203 | #define TX_DMA_EN BIT(0) |
| 204 | |
| 205 | #define PDMA_RST_IDX_REG 0x208 |
| 206 | #define RST_DRX_IDX0 BIT(16) |
| 207 | #define RST_DTX_IDX0 BIT(0) |
| 208 | |
| 209 | /* GDMA */ |
| 210 | #define GDMA_IG_CTRL_REG 0x000 |
| 211 | #define GDM_ICS_EN BIT(22) |
| 212 | #define GDM_TCS_EN BIT(21) |
| 213 | #define GDM_UCS_EN BIT(20) |
| 214 | #define STRP_CRC BIT(16) |
| 215 | #define MYMAC_DP_S 12 |
| 216 | #define MYMAC_DP_M 0xf000 |
| 217 | #define BC_DP_S 8 |
| 218 | #define BC_DP_M 0xf00 |
| 219 | #define MC_DP_S 4 |
| 220 | #define MC_DP_M 0xf0 |
| 221 | #define UN_DP_S 0 |
| 222 | #define UN_DP_M 0x0f |
| 223 | |
| 224 | #define GDMA_EG_CTRL_REG 0x004 |
| 225 | #define GDMA_CPU_BRIDGE_EN BIT(31) |
| 226 | |
| 227 | #define GDMA_MAC_LSB_REG 0x008 |
| 228 | |
| 229 | #define GDMA_MAC_MSB_REG 0x00c |
| 230 | |
| 231 | /* MYMAC_DP/BC_DP/MC_DP/UN_DP: Destination ports */ |
| 232 | #define DP_PDMA 0 |
| 233 | #define DP_GDMA1 1 |
| 234 | #define DP_GDMA2 2 |
| 235 | #define DP_PPE 4 |
| 236 | #define DP_QDMA 5 |
| 237 | #define DP_DISCARD 7 |
| 238 | |
| 239 | /* GMAC Registers */ |
| 240 | #define GMAC_PPSC_REG 0x0000 |
| 241 | #define PHY_MDC_CFG GENMASK(29, 24) |
| 242 | #define MDC_TURBO BIT(20) |
| 243 | #define MDC_MAX_FREQ 25000000 |
| 244 | #define MDC_MAX_DIVIDER 63 |
| 245 | |
| 246 | #define GMAC_PIAC_REG 0x0004 |
| 247 | #define PHY_ACS_ST BIT(31) |
| 248 | #define MDIO_REG_ADDR_S 25 |
| 249 | #define MDIO_REG_ADDR_M 0x3e000000 |
| 250 | #define MDIO_PHY_ADDR_S 20 |
| 251 | #define MDIO_PHY_ADDR_M 0x1f00000 |
| 252 | #define MDIO_CMD_S 18 |
| 253 | #define MDIO_CMD_M 0xc0000 |
| 254 | #define MDIO_ST_S 16 |
| 255 | #define MDIO_ST_M 0x30000 |
| 256 | #define MDIO_RW_DATA_S 0 |
| 257 | #define MDIO_RW_DATA_M 0xffff |
| 258 | |
| 259 | #define GMAC_XGMAC_STS_REG 0x000c |
| 260 | #define P1_XGMAC_FORCE_LINK BIT(15) |
| 261 | |
| 262 | #define GMAC_MAC_MISC_REG 0x0010 |
| 263 | #define MISC_MDC_TURBO BIT(4) |
| 264 | |
| 265 | #define GMAC_GSW_CFG_REG 0x0080 |
| 266 | #define GSWTX_IPG_M 0xF0000 |
| 267 | #define GSWTX_IPG_S 16 |
| 268 | #define GSWRX_IPG_M 0xF |
| 269 | #define GSWRX_IPG_S 0 |
| 270 | |
| 271 | /* MDIO_CMD: MDIO commands */ |
| 272 | #define MDIO_CMD_ADDR 0 |
| 273 | #define MDIO_CMD_WRITE 1 |
| 274 | #define MDIO_CMD_READ 2 |
| 275 | #define MDIO_CMD_READ_C45 3 |
| 276 | |
| 277 | /* MDIO_ST: MDIO start field */ |
| 278 | #define MDIO_ST_C45 0 |
| 279 | #define MDIO_ST_C22 1 |
| 280 | |
| 281 | #define GMAC_PORT_MCR(p) (0x0100 + (p) * 0x100) |
| 282 | #define MAC_RX_PKT_LEN_S 24 |
| 283 | #define MAC_RX_PKT_LEN_M 0x3000000 |
| 284 | #define IPG_CFG_S 18 |
| 285 | #define IPG_CFG_M 0xc0000 |
| 286 | #define MAC_MODE BIT(16) |
| 287 | #define FORCE_MODE BIT(15) |
| 288 | #define MAC_TX_EN BIT(14) |
| 289 | #define MAC_RX_EN BIT(13) |
| 290 | #define DEL_RXFIFO_CLR BIT(12) |
| 291 | #define BKOFF_EN BIT(9) |
| 292 | #define BACKPR_EN BIT(8) |
| 293 | #define FORCE_RX_FC BIT(5) |
| 294 | #define FORCE_TX_FC BIT(4) |
| 295 | #define FORCE_SPD_S 2 |
| 296 | #define FORCE_SPD_M 0x0c |
| 297 | #define FORCE_DPX BIT(1) |
| 298 | #define FORCE_LINK BIT(0) |
| 299 | |
| 300 | /* Values of IPG_CFG */ |
| 301 | #define IPG_96BIT 0 |
| 302 | #define IPG_96BIT_WITH_SHORT_IPG 1 |
| 303 | #define IPG_64BIT 2 |
| 304 | |
| 305 | /* MAC_RX_PKT_LEN: Max RX packet length */ |
| 306 | #define MAC_RX_PKT_LEN_1518 0 |
| 307 | #define MAC_RX_PKT_LEN_1536 1 |
| 308 | #define MAC_RX_PKT_LEN_1552 2 |
| 309 | #define MAC_RX_PKT_LEN_JUMBO 3 |
| 310 | |
| 311 | /* FORCE_SPD: Forced link speed */ |
| 312 | #define SPEED_10M 0 |
| 313 | #define SPEED_100M 1 |
| 314 | #define SPEED_1000M 2 |
| 315 | |
| 316 | #define GMAC_TRGMII_RCK_CTRL 0x300 |
| 317 | #define RX_RST BIT(31) |
| 318 | #define RXC_DQSISEL BIT(30) |
| 319 | |
| 320 | #define NUM_TRGMII_CTRL 5 |
| 321 | |
| 322 | #define GMAC_TRGMII_TD_ODT(n) (0x354 + (n) * 8) |
| 323 | #define TD_DM_DRVN_S 4 |
| 324 | #define TD_DM_DRVN_M 0xf0 |
| 325 | #define TD_DM_DRVP_S 0 |
| 326 | #define TD_DM_DRVP_M 0x0f |
| 327 | |
| 328 | /* XGMAC Status Registers */ |
| 329 | #define XGMAC_STS(x) (((x) == 2) ? 0x001C : 0x000C) |
| 330 | #define XGMAC_FORCE_LINK(x) (((x) == 1) ? BIT(31) : BIT(15)) |
| 331 | |
| 332 | /* XGMAC Registers */ |
| 333 | #define XGMAC_PORT_MCR(x) (0x2000 + (((x) - 1) * 0x1000)) |
| 334 | #define XGMAC_TRX_DISABLE 0xf |
| 335 | #define XGMAC_FORCE_TX_FC BIT(5) |
| 336 | #define XGMAC_FORCE_RX_FC BIT(4) |
| 337 | |
| 338 | /* MDIO Indirect Access Registers */ |
| 339 | #define MII_MMD_ACC_CTL_REG 0x0d |
| 340 | #define MMD_CMD_S 14 |
| 341 | #define MMD_CMD_M 0xc000 |
| 342 | #define MMD_DEVAD_S 0 |
| 343 | #define MMD_DEVAD_M 0x1f |
| 344 | |
| 345 | /* MMD_CMD: MMD commands */ |
| 346 | #define MMD_ADDR 0 |
| 347 | #define MMD_DATA 1 |
| 348 | #define MMD_DATA_RW_POST_INC 2 |
| 349 | #define MMD_DATA_W_POST_INC 3 |
| 350 | |
| 351 | #define MII_MMD_ADDR_DATA_REG 0x0e |
| 352 | |
| 353 | /* PDMA descriptors */ |
| 354 | struct mtk_rx_dma { |
| 355 | unsigned int rxd1; |
| 356 | unsigned int rxd2; |
| 357 | unsigned int rxd3; |
| 358 | unsigned int rxd4; |
| 359 | } __packed __aligned(4); |
| 360 | |
| 361 | struct mtk_rx_dma_v2 { |
| 362 | unsigned int rxd1; |
| 363 | unsigned int rxd2; |
| 364 | unsigned int rxd3; |
| 365 | unsigned int rxd4; |
| 366 | unsigned int rxd5; |
| 367 | unsigned int rxd6; |
| 368 | unsigned int rxd7; |
| 369 | unsigned int rxd8; |
| 370 | } __packed __aligned(4); |
| 371 | |
| 372 | struct mtk_tx_dma { |
| 373 | unsigned int txd1; |
| 374 | unsigned int txd2; |
| 375 | unsigned int txd3; |
| 376 | unsigned int txd4; |
| 377 | } __packed __aligned(4); |
| 378 | |
| 379 | struct mtk_tx_dma_v2 { |
| 380 | unsigned int txd1; |
| 381 | unsigned int txd2; |
| 382 | unsigned int txd3; |
| 383 | unsigned int txd4; |
| 384 | unsigned int txd5; |
| 385 | unsigned int txd6; |
| 386 | unsigned int txd7; |
| 387 | unsigned int txd8; |
| 388 | } __packed __aligned(4); |
| 389 | |
| 390 | /* PDMA TXD fields */ |
| 391 | #define PDMA_TXD2_DDONE BIT(31) |
| 392 | #define PDMA_TXD2_LS0 BIT(30) |
| 393 | #define PDMA_V1_TXD2_SDL0_M GENMASK(29, 16) |
| 394 | #define PDMA_V1_TXD2_SDL0_SET(_v) FIELD_PREP(PDMA_V1_TXD2_SDL0_M, (_v)) |
| 395 | #define PDMA_V2_TXD2_SDL0_M GENMASK(23, 8) |
| 396 | #define PDMA_V2_TXD2_SDL0_SET(_v) FIELD_PREP(PDMA_V2_TXD2_SDL0_M, (_v)) |
| 397 | |
| 398 | #define PDMA_V1_TXD4_FPORT_M GENMASK(27, 25) |
| 399 | #define PDMA_V1_TXD4_FPORT_SET(_v) FIELD_PREP(PDMA_V1_TXD4_FPORT_M, (_v)) |
| 400 | #define PDMA_V2_TXD4_FPORT_M GENMASK(27, 24) |
| 401 | #define PDMA_V2_TXD4_FPORT_SET(_v) FIELD_PREP(PDMA_V2_TXD4_FPORT_M, (_v)) |
| 402 | |
| 403 | #define PDMA_V2_TXD5_FPORT_M GENMASK(19, 16) |
| 404 | #define PDMA_V2_TXD5_FPORT_SET(_v) FIELD_PREP(PDMA_V2_TXD5_FPORT_M, (_v)) |
| 405 | |
| 406 | /* PDMA RXD fields */ |
| 407 | #define PDMA_RXD2_DDONE BIT(31) |
| 408 | #define PDMA_RXD2_LS0 BIT(30) |
| 409 | #define PDMA_V1_RXD2_PLEN0_M GENMASK(29, 16) |
| 410 | #define PDMA_V1_RXD2_PLEN0_GET(_v) FIELD_GET(PDMA_V1_RXD2_PLEN0_M, (_v)) |
| 411 | #define PDMA_V1_RXD2_PLEN0_SET(_v) FIELD_PREP(PDMA_V1_RXD2_PLEN0_M, (_v)) |
| 412 | #define PDMA_V2_RXD2_PLEN0_M GENMASK(23, 8) |
| 413 | #define PDMA_V2_RXD2_PLEN0_GET(_v) FIELD_GET(PDMA_V2_RXD2_PLEN0_M, (_v)) |
| 414 | #define PDMA_V2_RXD2_PLEN0_SET(_v) FIELD_PREP(PDMA_V2_RXD2_PLEN0_M, (_v)) |
| 415 | |
| 416 | void mtk_fe_rmw(struct mtk_eth_priv *priv, u32 reg, u32 clr, u32 set); |
| 417 | void mtk_gmac_rmw(struct mtk_eth_priv *priv, u32 reg, u32 clr, u32 set); |
| 418 | void mtk_ethsys_rmw(struct mtk_eth_priv *priv, u32 reg, u32 clr, u32 set); |
| 419 | |
| 420 | int mtk_mii_read(struct mtk_eth_priv *priv, u8 phy, u8 reg); |
| 421 | int mtk_mii_write(struct mtk_eth_priv *priv, u8 phy, u8 reg, u16 data); |
| 422 | int mtk_mmd_read(struct mtk_eth_priv *priv, u8 addr, u8 devad, u16 reg); |
| 423 | int mtk_mmd_write(struct mtk_eth_priv *priv, u8 addr, u8 devad, u16 reg, |
| 424 | u16 val); |
| 425 | int mtk_mmd_ind_read(struct mtk_eth_priv *priv, u8 addr, u8 devad, u16 reg); |
| 426 | int mtk_mmd_ind_write(struct mtk_eth_priv *priv, u8 addr, u8 devad, u16 reg, |
| 427 | u16 val); |
| 428 | |
| 429 | #endif /* _MTK_ETH_H_ */ |