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git01.mediatek.com / filogic / uboot / 29d247aa2a1f888836ec5a1282f6313cda44f5cf / . / arch / arm / dts / zynqmp-e-a2197-00-revA.dts
blob: bd0ba557e072748478b3f8ddf3d9def6ea010c24 [file] [log] [blame]
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * dts file for Xilinx Versal a2197 RevA System Controller
4 *
Saeed Nowshadi35a2cd62021-03-22 11:58:38 -0700[diff] [blame]5 * (C) Copyright 2019 - 2021, Xilinx, Inc.
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]6 *
7 * Michal Simek <michal.simek@xilinx.com>
8 */
9/dts-v1/;
10
11#include "zynqmp.dtsi"
12#include "zynqmp-clk-ccf.dtsi"
13#include <dt-bindings/gpio/gpio.h>
14#include <dt-bindings/phy/phy.h>
15
16/ {
17 model = "Versal System Controller on a2197 Eval board RevA"; /* VCK190/VMK180 */
18 compatible = "xlnx,zynqmp-e-a2197-00-revA", "xlnx,zynqmp-a2197-revA",
19 "xlnx,zynqmp-a2197", "xlnx,zynqmp";
20
21 aliases {
22 ethernet0 = &gem0;
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]23 i2c0 = &i2c0;
24 i2c1 = &i2c1;
25 mmc0 = &sdhci1;
Michal Simek53b145d2021-06-03 11:46:50 +0200[diff] [blame]26 nvmem0 = &eeprom;
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]27 rtc0 = &rtc;
28 serial0 = &uart0;
29 serial1 = &dcc;
30 };
31
32 chosen {
33 bootargs = "earlycon";
34 stdout-path = "serial0:115200n8";
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]35 };
36
37 memory@0 {
38 device_type = "memory";
39 reg = <0x0 0x0 0x0 0x80000000>;
40 };
41
42 ina226-vccint {
43 compatible = "iio-hwmon";
44 io-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>;
45 };
46 ina226-vcc-soc {
47 compatible = "iio-hwmon";
48 io-channels = <&vcc_soc 0>, <&vcc_soc 1>, <&vcc_soc 2>, <&vcc_soc 3>;
49 };
50 ina226-vcc-pmc {
51 compatible = "iio-hwmon";
52 io-channels = <&vcc_pmc 0>, <&vcc_pmc 1>, <&vcc_pmc 2>, <&vcc_pmc 3>;
53 };
54 ina226-vcc-ram {
55 compatible = "iio-hwmon";
56 io-channels = <&vcc_ram 0>, <&vcc_ram 1>, <&vcc_ram 2>, <&vcc_ram 3>;
57 };
58 ina226-vcc-pslp {
59 compatible = "iio-hwmon";
60 io-channels = <&vcc_pslp 0>, <&vcc_pslp 1>, <&vcc_pslp 2>, <&vcc_pslp 3>;
61 };
62 ina226-vcc-psfp {
63 compatible = "iio-hwmon";
64 io-channels = <&vcc_psfp 0>, <&vcc_psfp 1>, <&vcc_psfp 2>, <&vcc_psfp 3>;
65 };
66 ina226-vccaux {
67 compatible = "iio-hwmon";
68 io-channels = <&vccaux 0>, <&vccaux 1>, <&vccaux 2>, <&vccaux 3>;
69 };
70 ina226-vccaux-pmc {
71 compatible = "iio-hwmon";
72 io-channels = <&vccaux_pmc 0>, <&vccaux_pmc 1>, <&vccaux_pmc 2>, <&vccaux_pmc 3>;
73 };
74 ina226-vcco-500 {
75 compatible = "iio-hwmon";
76 io-channels = <&vcco_500 0>, <&vcco_500 1>, <&vcco_500 2>, <&vcco_500 3>;
77 };
78 ina226-vcco-501 {
79 compatible = "iio-hwmon";
80 io-channels = <&vcco_501 0>, <&vcco_501 1>, <&vcco_501 2>, <&vcco_501 3>;
81 };
82 ina226-vcco-502 {
83 compatible = "iio-hwmon";
84 io-channels = <&vcco_502 0>, <&vcco_502 1>, <&vcco_502 2>, <&vcco_502 3>;
85 };
86 ina226-vcco-503 {
87 compatible = "iio-hwmon";
88 io-channels = <&vcco_503 0>, <&vcco_503 1>, <&vcco_503 2>, <&vcco_503 3>;
89 };
90 ina226-vcc-1v8 {
91 compatible = "iio-hwmon";
92 io-channels = <&vcc_1v8 0>, <&vcc_1v8 1>, <&vcc_1v8 2>, <&vcc_1v8 3>;
93 };
94 ina226-vcc-3v3 {
95 compatible = "iio-hwmon";
96 io-channels = <&vcc_3v3 0>, <&vcc_3v3 1>, <&vcc_3v3 2>, <&vcc_3v3 3>;
97 };
98 ina226-vcc-1v2-ddr4 {
99 compatible = "iio-hwmon";
100 io-channels = <&vcc_1v2_ddr4 0>, <&vcc_1v2_ddr4 1>, <&vcc_1v2_ddr4 2>, <&vcc_1v2_ddr4 3>;
101 };
102 ina226-vcc-1v1-lp4 {
103 compatible = "iio-hwmon";
104 io-channels = <&vcc1v1_lp4 0>, <&vcc1v1_lp4 1>, <&vcc1v1_lp4 2>, <&vcc1v1_lp4 3>;
105 };
106 ina226-vadj-fmc {
107 compatible = "iio-hwmon";
108 io-channels = <&vadj_fmc 0>, <&vadj_fmc 1>, <&vadj_fmc 2>, <&vadj_fmc 3>;
109 };
110 ina226-mgtyavcc {
111 compatible = "iio-hwmon";
112 io-channels = <&mgtyavcc 0>, <&mgtyavcc 1>, <&mgtyavcc 2>, <&mgtyavcc 3>;
113 };
114 ina226-mgtyavtt {
115 compatible = "iio-hwmon";
116 io-channels = <&mgtyavtt 0>, <&mgtyavtt 1>, <&mgtyavtt 2>, <&mgtyavtt 3>;
117 };
118 ina226-mgtyvccaux {
119 compatible = "iio-hwmon";
120 io-channels = <&mgtyvccaux 0>, <&mgtyvccaux 1>, <&mgtyvccaux 2>, <&mgtyvccaux 3>;
121 };
122};
123
124&uart0 { /* uart0 MIO38-39 */
125 status = "okay";
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]126};
127
128&sdhci1 { /* sd1 MIO45-51 cd in place */
129 status = "okay";
130 no-1-8-v;
131 disable-wp;
Michal Simek3b662642020-07-22 17:42:43 +0200[diff] [blame]132 xlnx,mio-bank = <1>;
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]133};
134
135&gem0 {
136 status = "okay";
137 phy-handle = <&phy0>;
138 phy-mode = "sgmii";
139 is-internal-pcspma;
140 phy0: ethernet-phy@0 { /* u131 M88E1512 */
141 reg = <0>;
142 };
143};
144
145&gpio {
146 status = "okay";
147 gpio-line-names = "", "", "", "", "", /* 0 - 4 */
148 "", "", "DC_SYS_CTRL0", "DC_SYS_CTRL1", "DC_SYS_CTRL2", /* 5 - 9 */
149 "DC_SYS_CTRL3", "ZU4_TRIGGER", "SYSCTLR_PB", "", "", /* 10 - 14 */
150 "", "", "", "", "", /* 15 - 19 */
151 "", "", "", "", "", /* 20 - 24 */
152 "", "", "", "", "", /* 25 - 29 */
153 "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */
154 "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */
155 "", "", "ETH_RESET_B", "", "", /* 40 - 44 */
156 "SD1_CD_B", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */
157 "SD1_CMD", "SD1_CLK", "", "", "", /* 50 - 54 */
158 "", "", "", "", "", /* 55 - 59 */
159 "", "", "", "", "", /* 60 - 64 */
160 "", "", "", "", "", /* 65 - 69 */
161 "", "", "", "", "", /* 70 - 74 */
162 "", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */
Saeed Nowshadi893180e2020-03-27 08:12:20 -0700[diff] [blame]163 "SYSCTLR_VERSAL_MODE0", "SYSCTLR_VERSAL_MODE1", /* 78 - 79 */
Saeed Nowshadi342c3cd2021-04-13 16:01:42 -0700[diff] [blame]164 "SYSCTLR_VERSAL_MODE2", "SYSCTLR_VERSAL_MODE3", "SYSCTLR_POR_B_LS", "DC_PRSNT", "", /* 80 - 84 */
165 "SYSCTLR_JTAG_S0", "SYSCTLR_JTAG_S1", "SYSCTLR_IIC_MUX0_RESET_B", "SYSCTLR_IIC_MUX1_RESET_B", "", /* 85 - 89 */
166 "SYSCTLR_GPIO0", "SYSCTLR_GPIO1", "SYSCTLR_GPIO2", "SYSCTLR_GPIO3", "SYSCTLR_GPIO4", /* 90 - 94 */
167 "SYSCTLR_GPIO5", "", "", "", "", /* 95 - 99 */
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]168 "", "", "", "", "", /* 100 - 104 */
169 "", "", "", "", "", /* 105 - 109 */
170 "", "", "", "", "", /* 110 - 114 */
171 "", "", "", "", "", /* 115 - 119 */
172 "", "", "", "", "", /* 120 - 124 */
173 "", "", "", "", "", /* 125 - 129 */
Saeed Nowshadi342c3cd2021-04-13 16:01:42 -0700[diff] [blame]174 "PMBUS1_INA226_ALERT", "PMBUS2_INA226_ALERT", "", "", "", /* 130 - 134 */
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]175 "", "", "", "", "", /* 135 - 139 */
Saeed Nowshadi342c3cd2021-04-13 16:01:42 -0700[diff] [blame]176 "PMBUS_ALERT", "", "SYSCTLR_ETH_RESET_B", "SYSCTLR_VCC0V85_TG", "MAX6643_OT_B", /* 140 - 144 */
177 "MAX6643_FANFINAL_B", "MAX6643_FULLSPD", "", "", "", /* 145 - 149 */
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]178 "", "", "", "", "", /* 150 - 154 */
179 "", "", "", "", "", /* 155 - 159 */
180 "", "", "", "", "", /* 160 - 164 */
181 "", "", "", "", "", /* 165 - 169 */
182 "", "", "", ""; /* 170 - 174 */
183};
184
185&i2c0 { /* MIO 34-35 - can't stay here */
186 status = "okay";
187 clock-frequency = <400000>;
188 i2c-mux@74 { /* u33 */
189 compatible = "nxp,pca9548";
190 #address-cells = <1>;
191 #size-cells = <0>;
192 reg = <0x74>;
193 /* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */
194 i2c@0 { /* PMBUS */
195 #address-cells = <1>;
196 #size-cells = <0>;
197 reg = <0>;
198 /* u152 IR35215 0x16/0x46 vcc_soc */
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]199 /* u179 ir38164 0x19/0x49 vcco_500 */
200 /* u181 ir38164 0x1a/0x4a vcco_501 */
201 /* u183 ir38164 0x1b/0x4b vcco_502 */
202 /* u185 ir38164 0x1e/0x4e vadj_fmc */
203 /* u187 ir38164 0x1F/0x4f mgtyavcc */
204 /* u189 ir38164 0x20/0x50 mgtyavtt */
205 /* u194 ir38164 0x13/0x43 vdd1_1v8_lp4 */
206 /* u195 ir38164 0x14/0x44 vdd2_1v8_lp4 */
Michal Simek3514e4e2020-03-30 11:35:38 +0200[diff] [blame]207
208 irps5401_47: irps5401@47 { /* IRPS5401 - u160 */
209 compatible = "infineon,irps5401";
210 reg = <0x47>; /* pmbus / i2c 0x17 */
211 };
212 irps5401_4c: irps5401@4c { /* IRPS5401 - u167 */
213 compatible = "infineon,irps5401";
214 reg = <0x4c>; /* pmbus / i2c 0x1c */
215 };
216 irps5401_4d: irps5401@4d { /* IRPS5401 - u175 */
217 compatible = "infineon,irps5401";
218 reg = <0x4d>; /* pmbus / i2c 0x1d */
219 };
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]220 };
221 i2c@1 { /* PMBUS1_INA226 */
222 #address-cells = <1>;
223 #size-cells = <0>;
224 reg = <1>;
225 /* FIXME check alerts coming to SC */
226 vccint: ina226@40 { /* u65 */
227 compatible = "ti,ina226";
228 #io-channel-cells = <1>;
229 label = "ina226-vccint";
230 reg = <0x40>;
Saeed Nowshadi34cd5f82020-08-03 23:24:05 -0700[diff] [blame]231 shunt-resistor = <500>; /* R440 */
232 /* 0.80V @ 32A 1 of 6 Phases*/
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]233 };
234 vcc_soc: ina226@41 { /* u161 */
235 compatible = "ti,ina226";
236 #io-channel-cells = <1>;
237 label = "ina226-vcc-soc";
238 reg = <0x41>;
Saeed Nowshadi34cd5f82020-08-03 23:24:05 -0700[diff] [blame]239 shunt-resistor = <500>; /* R1702 */
240 /* 0.80V @ 18A */
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]241 };
242 vcc_pmc: ina226@42 { /* u163 */
243 compatible = "ti,ina226";
244 #io-channel-cells = <1>;
245 label = "ina226-vcc-pmc";
246 reg = <0x42>;
247 shunt-resistor = <5000>; /* R1214 */
248 /* 0.78V @ 500mA */
249 };
250 vcc_ram: ina226@43 { /* u162 */
251 compatible = "ti,ina226";
252 #io-channel-cells = <1>;
253 label = "ina226-vcc-ram";
254 reg = <0x43>;
255 shunt-resistor = <5000>; /* r1221 */
256 /* 0.78V @ 4A */
257 };
258 vcc_pslp: ina226@44 { /* u165 */
259 compatible = "ti,ina226";
260 #io-channel-cells = <1>;
261 label = "ina226-vcc-pslp";
262 reg = <0x44>;
263 shunt-resistor = <5000>; /* R1216 */
264 /* 0.78V @ 1A */
265 };
266 vcc_psfp: ina226@45 { /* u164 */
267 compatible = "ti,ina226";
268 #io-channel-cells = <1>;
269 label = "ina226-vcc-psfp";
270 reg = <0x45>;
271 shunt-resistor = <5000>; /* R1219 */
272 /* 0.78V @ 2A */
273 };
274 };
275 i2c@2 { /* PCIE_CLK */
276 #address-cells = <1>;
277 #size-cells = <0>;
278 reg = <2>;
279 clock_8t49n287: clock-generator@d8 { /* u39 8T49N240 */
280 #clock-cells = <1>; /* author David Cater <david.cater@idt.com>*/
281 compatible = "idt,8t49n240", "idt,8t49n241"; /* FIXME no driver for 240 */
282 reg = <0xd8>;
283 /* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */
284 /* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */
285 };
286 };
287 i2c@3 { /* PMBUS2_INA226 */
288 #address-cells = <1>;
289 #size-cells = <0>;
290 reg = <3>;
291 /* FIXME check alerts coming to SC */
292 vccaux: ina226@40 { /* u166 */
293 compatible = "ti,ina226";
294 #io-channel-cells = <1>;
295 label = "ina226-vccaux";
296 reg = <0x40>;
297 shunt-resistor = <5000>; /* R382 */
298 /* 1.5V @ 3A */
299 };
300 vccaux_pmc: ina226@41 { /* u168 */
301 compatible = "ti,ina226";
302 #io-channel-cells = <1>;
303 label = "ina226-vccaux-pmc";
304 reg = <0x41>;
305 shunt-resistor = <5000>; /* R1246 */
306 /* 1.5V @ 500mA */
307 };
308 vcco_500: ina226@42 { /* u178 */
309 compatible = "ti,ina226";
310 #io-channel-cells = <1>;
311 label = "ina226-vcco-500";
312 reg = <0x42>;
313 shunt-resistor = <2000>; /* R1300 */
314 /* 3.3V @ 5A */
315 };
316 vcco_501: ina226@43 { /* u180 */
317 compatible = "ti,ina226";
318 #io-channel-cells = <1>;
319 label = "ina226-vcco-501";
320 reg = <0x43>;
321 shunt-resistor = <2000>; /* R1313 */
322 /* 3.3V @ 5A */
323 };
324 vcco_502: ina226@44 { /* u182 */
325 compatible = "ti,ina226";
326 #io-channel-cells = <1>;
327 label = "ina226-vcco-502";
328 reg = <0x44>;
329 shunt-resistor = <2000>; /* R1330 */
330 /* 3.3V @ 5A */
331 };
332 vcco_503: ina226@45 { /* u172 */
333 compatible = "ti,ina226";
334 #io-channel-cells = <1>;
335 label = "ina226-vcco-503";
336 reg = <0x45>;
337 shunt-resistor = <5000>; /* R1229 */
338 /* 1.8V @ 2A */
339 };
340 vcc_1v8: ina226@46 { /* u173 */
341 compatible = "ti,ina226";
342 #io-channel-cells = <1>;
343 label = "ina226-vcc-1v8";
344 reg = <0x46>;
345 shunt-resistor = <5000>; /* R400 */
346 /* 1.8V @ 6A */
347 };
348 vcc_3v3: ina226@47 { /* u174 */
349 compatible = "ti,ina226";
350 #io-channel-cells = <1>;
351 label = "ina226-vcc-3v3";
352 reg = <0x47>;
353 shunt-resistor = <5000>; /* R1232 */
354 /* 3.3V @ 500mA */
355 };
356 vcc_1v2_ddr4: ina226@48 { /* u176 */
357 compatible = "ti,ina226";
358 #io-channel-cells = <1>;
359 label = "ina226-vcc-1v2-ddr4";
360 reg = <0x48>;
361 shunt-resistor = <5000>; /* R1275 */
362 /* 1.2V @ 4A */
363 };
364 vcc1v1_lp4: ina226@49 { /* u177 */
365 compatible = "ti,ina226";
366 #io-channel-cells = <1>;
367 label = "ina226-vcc1v1-lp4";
368 reg = <0x49>;
369 shunt-resistor = <5000>; /* R1286 */
370 /* 1.1V @ 4A */
371 };
372 vadj_fmc: ina226@4a { /* u184 */
373 compatible = "ti,ina226";
374 #io-channel-cells = <1>;
375 label = "ina226-vadj-fmc";
376 reg = <0x4a>;
377 shunt-resistor = <2000>; /* R1350 */
378 /* 1.5V @ 10A */
379 };
380 mgtyavcc: ina226@4b { /* u186 */
381 compatible = "ti,ina226";
382 #io-channel-cells = <1>;
383 label = "ina226-mgtyavcc";
384 reg = <0x4b>;
385 shunt-resistor = <2000>; /* R1367 */
386 /* 0.88V @ 6A */
387 };
388 mgtyavtt: ina226@4c { /* u188 */
389 compatible = "ti,ina226";
390 #io-channel-cells = <1>;
391 label = "ina226-mgtyavtt";
392 reg = <0x4c>;
393 shunt-resistor = <2000>; /* R1384 */
394 /* 1.2V @ 10A */
395 };
396 mgtyvccaux: ina226@4d { /* u234 */
397 compatible = "ti,ina226";
398 #io-channel-cells = <1>;
399 label = "ina226-mgtyvccaux";
400 reg = <0x4d>;
401 shunt-resistor = <5000>; /* r1679 */
402 /* 1.5V @ 500mA */
403 };
404 };
405 i2c@4 { /* LP_I2C_SM */
406 #address-cells = <1>;
407 #size-cells = <0>;
408 reg = <4>;
409 /* FIXME wires ready but chip is missing */
410 };
411 i2c@5 { /* zSFP_SI570 */
412 #address-cells = <1>;
413 #size-cells = <0>;
414 reg = <5>;
415 si570_zsfp: clock-generator@5d { /* u192 */
416 #clock-cells = <0>;
417 compatible = "silabs,si570";
418 reg = <0x5d>;
419 temperature-stability = <50>;
420 factory-fout = <156250000>;
421 clock-frequency = <156250000>;
Saeed Nowshadi9a34a4b2020-03-04 10:21:34 -0800[diff] [blame]422 clock-output-names = "si570_zsfp_clk";
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]423 };
424 };
425 i2c@6 { /* USER_SI570_1 */
426 #address-cells = <1>;
427 #size-cells = <0>;
428 reg = <6>;
Saeed Nowshadi9a34a4b2020-03-04 10:21:34 -0800[diff] [blame]429 si570_user1: clock-generator@5d { /* u205 */
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]430 #clock-cells = <0>;
431 compatible = "silabs,si570";
432 reg = <0x5f>;
433 temperature-stability = <50>;
434 factory-fout = <100000000>;
435 clock-frequency = <100000000>;
436 clock-output-names = "si570_user1";
437 };
438
439 };
440 i2c@7 { /* USER_SI570_2 */
441 #address-cells = <1>;
442 #size-cells = <0>;
443 reg = <7>;
444 /* FIXME wires ready but chip is missing */
445 };
446 };
447};
448
449&i2c1 { /* i2c1 MIO 36-37 */
450 status = "okay";
451 clock-frequency = <400000>;
452
453 i2c-mux@74 { /* u35 */
454 compatible = "nxp,pca9548";
455 #address-cells = <1>;
456 #size-cells = <0>;
457 reg = <0x74>;
Raviteja Narayanam574fa192021-04-01 07:14:10 -0600[diff] [blame]458 i2c-mux-idle-disconnect;
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]459 /* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */
460 dc_i2c: i2c@0 { /* DC_I2C */
461 #address-cells = <1>;
462 #size-cells = <0>;
463 reg = <0>;
464 /* Use for storing information about SC board */
465 eeprom: eeprom@54 { /* u34 - m24128 16kB */
466 compatible = "st,24c128", "atmel,24c128";
467 reg = <0x54>; /* 0x5c too */
468 };
469 si570_ref_clk: clock-generator@5d { /* u32 */
470 #clock-cells = <0>;
471 compatible = "silabs,si570";
472 reg = <0x5d>;
473 temperature-stability = <50>;
474 factory-fout = <33333333>;
475 clock-frequency = <33333333>;
476 clock-output-names = "ref_clk";
Michal Simekf86d2b52021-03-09 12:43:42 +0100[diff] [blame]477 silabs,skip-recall;
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]478 };
479 /* and connector J212D */
480 };
481 fmc1: i2c@1 { /* FMCP1_IIC */
482 #address-cells = <1>;
483 #size-cells = <0>;
484 reg = <1>;
485 /* FIXME connection to Samtec J51C */
486 /* expected eeprom 0x50 FMC cards */
487 };
488 fmc2: i2c@2 { /* FMCP2_IIC */
489 #address-cells = <1>;
490 #size-cells = <0>;
491 reg = <2>;
492 /* FIXME connection to Samtec J53C */
493 /* expected eeprom 0x50 FMC cards */
494 };
495 i2c@3 { /* DDR4_DIMM1 */
496 #address-cells = <1>;
497 #size-cells = <0>;
498 reg = <3>;
499 si570_ddr_dimm1: clock-generator@60 { /* u2 */
500 #clock-cells = <0>;
501 compatible = "silabs,si570";
502 reg = <0x60>;
503 temperature-stability = <50>;
504 factory-fout = <200000000>;
505 clock-frequency = <200000000>;
506 clock-output-names = "si570_ddrdimm1_clk";
Saeed Nowshadi35a2cd62021-03-22 11:58:38 -0700[diff] [blame]507 silabs,skip-recall;
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]508 };
509 };
510 i2c@4 { /* LPDDR4_SI570_CLK2 */
511 #address-cells = <1>;
512 #size-cells = <0>;
513 reg = <4>;
Saeed Nowshadi9a34a4b2020-03-04 10:21:34 -0800[diff] [blame]514 si570_lpddr4clk2: clock-generator@60 { /* u3 */
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]515 #clock-cells = <0>;
516 compatible = "silabs,si570";
517 reg = <0x60>;
518 temperature-stability = <50>;
519 factory-fout = <200000000>;
520 clock-frequency = <200000000>;
521 clock-output-names = "si570_lpddr4_clk2";
522 };
523 };
524 i2c@5 { /* LPDDR4_SI570_CLK1 */
525 #address-cells = <1>;
526 #size-cells = <0>;
527 reg = <5>;
Saeed Nowshadi9a34a4b2020-03-04 10:21:34 -0800[diff] [blame]528 si570_lpddr4clk1: clock-generator@60 { /* u4 */
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]529 #clock-cells = <0>;
530 compatible = "silabs,si570";
531 reg = <0x60>;
532 temperature-stability = <50>;
533 factory-fout = <200000000>;
534 clock-frequency = <200000000>;
535 clock-output-names = "si570_lpddr4_clk1";
536 };
537 };
538 i2c@6 { /* HSDP_SI570 */
539 #address-cells = <1>;
540 #size-cells = <0>;
541 reg = <6>;
542 si570_hsdp: clock-generator@5d { /* u5 */
543 #clock-cells = <0>;
544 compatible = "silabs,si570";
545 reg = <0x5d>;
546 temperature-stability = <50>;
547 factory-fout = <156250000>;
548 clock-frequency = <156250000>;
549 clock-output-names = "si570_hsdp_clk";
550 };
551 };
552 i2c@7 { /* 8A34001 - U219B and J310 connector */
553 #address-cells = <1>;
554 #size-cells = <0>;
555 reg = <7>;
556 };
557 };
Saeed Nowshadic06192e2020-08-03 23:24:04 -0700[diff] [blame]558 i2c-mux@75 { /* u214 */
559 compatible = "nxp,pca9548";
560 #address-cells = <1>;
561 #size-cells = <0>;
562 reg = <0x75>;
Raviteja Narayanam574fa192021-04-01 07:14:10 -0600[diff] [blame]563 i2c-mux-idle-disconnect;
Saeed Nowshadic06192e2020-08-03 23:24:04 -0700[diff] [blame]564 i2c@0 { /* SFP0_IIC */
565 #address-cells = <1>;
566 #size-cells = <0>;
567 reg = <0>;
568 /* SFP0 */
569 };
570 i2c@1 { /* SFP1_IIC */
571 #address-cells = <1>;
572 #size-cells = <0>;
573 reg = <1>;
574 /* SFP1 */
575 };
576 i2c@2 { /* QSFP1_I2C */
577 #address-cells = <1>;
578 #size-cells = <0>;
579 reg = <2>;
580 /* QSFP1 */
581 };
582 /* 3 - 7 unused */
583 };
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]584};
585
586&xilinx_ams {
587 status = "okay";
588};
589
590&ams_ps {
591 status = "okay";
592};
593
594&ams_pl {
595 status = "okay";
596};