| Stefan Roese | a6f2ea4 | 2020-06-30 12:08:58 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| 2 | /* |
| 3 | * Copyright (C) 2019-2020 |
| 4 | * Marvell <www.marvell.com> |
| 5 | */ |
| 6 | |
| 7 | #ifndef __OCTEON_COMMON_H__ |
| 8 | #define __OCTEON_COMMON_H__ |
| 9 | |
| Stefan Roese | 82ba278 | 2020-09-02 08:29:10 +0200 | [diff] [blame] | 10 | #if defined(CONFIG_RAM_OCTEON) |
| 11 | #define CONFIG_SYS_MALLOC_LEN (16 << 20) |
| 12 | #define CONFIG_SYS_INIT_SP_OFFSET 0x20100000 |
| 13 | #else |
| 14 | /* No DDR init -> run in L2 cache with limited resources */ |
| Stefan Roese | a6f2ea4 | 2020-06-30 12:08:58 +0200 | [diff] [blame] | 15 | #define CONFIG_SYS_MALLOC_LEN (256 << 10) |
| Stefan Roese | 82ba278 | 2020-09-02 08:29:10 +0200 | [diff] [blame] | 16 | #define CONFIG_SYS_INIT_SP_OFFSET 0x00180000 |
| 17 | #endif |
| 18 | |
| Stefan Roese | a6f2ea4 | 2020-06-30 12:08:58 +0200 | [diff] [blame] | 19 | #define CONFIG_SYS_SDRAM_BASE 0xffffffff80000000 |
| 20 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE |
| 21 | |
| 22 | #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + (1 << 20)) |
| 23 | |
| Stefan Roese | f70df7f | 2020-08-20 07:22:04 +0200 | [diff] [blame] | 24 | #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */ |
| 25 | |
| Stefan Roese | a6f2ea4 | 2020-06-30 12:08:58 +0200 | [diff] [blame] | 26 | #endif /* __OCTEON_COMMON_H__ */ |