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git01.mediatek.com / filogic / uboot / 2997122c82d49e6f46e5e8283784623e880ba404 / . / configs / minnowmax_defconfig
blob: efb9c1ef3146742284b61885b384487b32b56535 [file] [log] [blame]
Simon Glass4a56f102015-01-27 22:13:47 -0700[diff] [blame]1CONFIG_X86=y
Bin Meng03b341b2015-04-27 23:22:24 +0800[diff] [blame]2CONFIG_VENDOR_INTEL=y
Simon Glass4a56f102015-01-27 22:13:47 -0700[diff] [blame]3CONFIG_DEFAULT_DEVICE_TREE="minnowmax"
Joe Hershbergera274ded2015-05-12 14:46:24 -0500[diff] [blame]4CONFIG_TARGET_MINNOWMAX=y
5CONFIG_HAVE_INTEL_ME=y
Bin Meng9582ad52015-10-11 21:37:44 -0700[diff] [blame]6CONFIG_ENABLE_MRC_CACHE=y
Joe Hershbergera274ded2015-05-12 14:46:24 -0500[diff] [blame]7CONFIG_SMP=y
Bin Meng519dee02015-07-09 18:37:40 +0800[diff] [blame]8CONFIG_HAVE_VGA_BIOS=y
Simon Glass7133c392015-08-13 10:36:16 -0600[diff] [blame]9CONFIG_GENERATE_PIRQ_TABLE=y
10CONFIG_GENERATE_MP_TABLE=y
Simon Glasse3ee2fb2016-02-22 22:55:43 -0700[diff] [blame]11CONFIG_FIT=y
12CONFIG_FIT_SIGNATURE=y
Simon Glassc08ebf62016-02-22 22:55:40 -0700[diff] [blame]13CONFIG_BOOTSTAGE=y
14CONFIG_BOOTSTAGE_REPORT=y
Simon Glass1eaaf6c2015-04-29 22:26:03 -0600[diff] [blame]15CONFIG_CMD_CPU=y
Joe Hershberger5a9d7f12015-06-22 16:15:30 -0500[diff] [blame]16# CONFIG_CMD_IMLS is not set
17# CONFIG_CMD_FLASH is not set
Thomas Chou3a077cd2015-11-11 21:39:33 +0800[diff] [blame]18CONFIG_CMD_GPIO=y
Joe Hershberger5a9d7f12015-06-22 16:15:30 -0500[diff] [blame]19# CONFIG_CMD_SETEXPR is not set
20# CONFIG_CMD_NFS is not set
Joe Hershberger17491a82015-06-22 16:15:29 -0500[diff] [blame]21CONFIG_CMD_BOOTSTAGE=y
Joe Hershbergera274ded2015-05-12 14:46:24 -0500[diff] [blame]22CONFIG_OF_CONTROL=y
Simon Glassfb8757b2016-03-11 22:07:14 -0700[diff] [blame]23CONFIG_REGMAP=y
24CONFIG_SYSCON=y
Joe Hershbergera274ded2015-05-12 14:46:24 -0500[diff] [blame]25CONFIG_CPU=y
Joe Hershberger17491a82015-06-22 16:15:29 -0500[diff] [blame]26CONFIG_SPI_FLASH=y
Bin Meng27f5b192015-11-25 05:34:54 -0800[diff] [blame]27CONFIG_SPI_FLASH_GIGADEVICE=y
28CONFIG_SPI_FLASH_MACRONIX=y
29CONFIG_SPI_FLASH_STMICRO=y
30CONFIG_SPI_FLASH_WINBOND=y
Simon Glass31238dd2015-08-10 22:02:53 -0600[diff] [blame]31CONFIG_DM_ETH=y
Bin Meng29971222016-03-21 06:47:42 -0700[diff] [blame^]32CONFIG_RTL8169=y
Bin Meng63c10982015-09-28 05:14:15 -0700[diff] [blame]33CONFIG_DM_PCI=y
34CONFIG_DM_RTC=y
Simon Glassecab8fa2015-08-10 22:02:52 -0600[diff] [blame]35CONFIG_DEBUG_UART=y
36CONFIG_DEBUG_UART_BASE=0x3f8
37CONFIG_DEBUG_UART_CLOCK=1843200
Thomas Choua6cec012015-11-19 21:48:14 +0800[diff] [blame]38CONFIG_SYS_NS16550=y
Bin Meng72a049d2015-11-25 05:34:53 -0800[diff] [blame]39CONFIG_ICH_SPI=y
Bin Meng38de0202015-11-13 00:11:22 -0800[diff] [blame]40CONFIG_TIMER=y
Bin Meng63c10982015-09-28 05:14:15 -0700[diff] [blame]41CONFIG_USB=y
42CONFIG_DM_USB=y
Joe Hershberger17491a82015-06-22 16:15:29 -0500[diff] [blame]43CONFIG_VIDEO_VESA=y
44CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
45CONFIG_FRAMEBUFFER_VESA_MODE_11A=y
46CONFIG_USE_PRIVATE_LIBGCC=y