blob: 03c747b373b1aab317f760d4bd07c3083006dd57 [file] [log] [blame]
Marek Vasutc31c4b12018-10-02 22:31:47 +02001// SPDX-License-Identifier: GPL-2.0
2/*
3 * Renesas RCar Gen3 USB PHY driver
4 *
5 * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
6 */
7
Tom Riniabb9a042024-05-18 20:20:43 -06008#include <common.h>
Marek Vasutc31c4b12018-10-02 22:31:47 +02009#include <clk.h>
10#include <div64.h>
11#include <dm.h>
12#include <fdtdec.h>
13#include <generic-phy.h>
Simon Glass9bc15642020-02-03 07:36:16 -070014#include <malloc.h>
Marek Vasutc31c4b12018-10-02 22:31:47 +020015#include <reset.h>
16#include <syscon.h>
17#include <usb.h>
18#include <asm/io.h>
19#include <linux/bitops.h>
Simon Glassbdd5f812023-09-14 18:21:46 -060020#include <linux/printk.h>
Marek Vasutc31c4b12018-10-02 22:31:47 +020021#include <power/regulator.h>
22
23/* USB2.0 Host registers (original offset is +0x200) */
24#define USB2_INT_ENABLE 0x000
25#define USB2_USBCTR 0x00c
26#define USB2_SPD_RSM_TIMSET 0x10c
27#define USB2_OC_TIMSET 0x110
28#define USB2_COMMCTRL 0x600
29#define USB2_OBINTSTA 0x604
30#define USB2_OBINTEN 0x608
31#define USB2_VBCTRL 0x60c
32#define USB2_LINECTRL1 0x610
33#define USB2_ADPCTRL 0x630
34
35/* USBCTR */
36#define USB2_USBCTR_PLL_RST BIT(1)
37
38/* SPD_RSM_TIMSET */
39#define USB2_SPD_RSM_TIMSET_INIT 0x014e029b
40
41/* OC_TIMSET */
42#define USB2_OC_TIMSET_INIT 0x000209ab
43
44/* COMMCTRL */
45#define USB2_COMMCTRL_OTG_PERI BIT(31) /* 1 = Peripheral mode */
46
47/* LINECTRL1 */
48#define USB2_LINECTRL1_DP_RPD BIT(18)
49#define USB2_LINECTRL1_DM_RPD BIT(16)
50
51/* ADPCTRL */
52#define USB2_ADPCTRL_DRVVBUS BIT(4)
53
54struct rcar_gen3_phy {
55 fdt_addr_t regs;
56 struct clk clk;
57 struct udevice *vbus_supply;
58};
59
60static int rcar_gen3_phy_phy_init(struct phy *phy)
61{
62 struct rcar_gen3_phy *priv = dev_get_priv(phy->dev);
63
64 /* Initialize USB2 part */
65 writel(0, priv->regs + USB2_INT_ENABLE);
66 writel(USB2_SPD_RSM_TIMSET_INIT, priv->regs + USB2_SPD_RSM_TIMSET);
67 writel(USB2_OC_TIMSET_INIT, priv->regs + USB2_OC_TIMSET);
68
69 setbits_le32(priv->regs + USB2_LINECTRL1,
70 USB2_LINECTRL1_DP_RPD | USB2_LINECTRL1_DM_RPD);
71
72 clrbits_le32(priv->regs + USB2_COMMCTRL, USB2_COMMCTRL_OTG_PERI);
73
74 setbits_le32(priv->regs + USB2_ADPCTRL, USB2_ADPCTRL_DRVVBUS);
75
76 return 0;
77}
78
79static int rcar_gen3_phy_phy_power_on(struct phy *phy)
80{
81 struct rcar_gen3_phy *priv = dev_get_priv(phy->dev);
82 int ret;
83
84 if (priv->vbus_supply) {
85 ret = regulator_set_enable(priv->vbus_supply, true);
86 if (ret)
87 return ret;
88 }
89
90 setbits_le32(priv->regs + USB2_USBCTR, USB2_USBCTR_PLL_RST);
91 clrbits_le32(priv->regs + USB2_USBCTR, USB2_USBCTR_PLL_RST);
92
93 return 0;
94}
95
96static int rcar_gen3_phy_phy_power_off(struct phy *phy)
97{
98 struct rcar_gen3_phy *priv = dev_get_priv(phy->dev);
99
100 if (!priv->vbus_supply)
101 return 0;
102
103 return regulator_set_enable(priv->vbus_supply, false);
104}
105
106static const struct phy_ops rcar_gen3_phy_phy_ops = {
107 .init = rcar_gen3_phy_phy_init,
108 .power_on = rcar_gen3_phy_phy_power_on,
109 .power_off = rcar_gen3_phy_phy_power_off,
110};
111
112static int rcar_gen3_phy_probe(struct udevice *dev)
113{
114 struct rcar_gen3_phy *priv = dev_get_priv(dev);
115 int ret;
116
117 priv->regs = dev_read_addr(dev);
118 if (priv->regs == FDT_ADDR_T_NONE)
119 return -EINVAL;
120
121 ret = device_get_supply_regulator(dev, "vbus-supply",
122 &priv->vbus_supply);
123 if (ret && ret != -ENOENT) {
124 pr_err("Failed to get PHY regulator\n");
125 return ret;
126 }
127
128 /* Enable clock */
129 ret = clk_get_by_index(dev, 0, &priv->clk);
130 if (ret)
131 return ret;
132
133 ret = clk_enable(&priv->clk);
134 if (ret)
135 return ret;
136
137 return 0;
138}
139
140static int rcar_gen3_phy_remove(struct udevice *dev)
141{
142 struct rcar_gen3_phy *priv = dev_get_priv(dev);
143
144 clk_disable(&priv->clk);
Marek Vasutc31c4b12018-10-02 22:31:47 +0200145
146 return 0;
147}
148
149static const struct udevice_id rcar_gen3_phy_of_match[] = {
150 { .compatible = "renesas,rcar-gen3-usb2-phy", },
151 { },
152};
153
154U_BOOT_DRIVER(rcar_gen3_phy) = {
155 .name = "rcar-gen3-phy",
156 .id = UCLASS_PHY,
157 .of_match = rcar_gen3_phy_of_match,
158 .ops = &rcar_gen3_phy_phy_ops,
159 .probe = rcar_gen3_phy_probe,
160 .remove = rcar_gen3_phy_remove,
Simon Glass8a2b47f2020-12-03 16:55:17 -0700161 .priv_auto = sizeof(struct rcar_gen3_phy),
Marek Vasutc31c4b12018-10-02 22:31:47 +0200162};