blob: f707cc30973990f83b1e2b2a58410acf509a3839 [file] [log] [blame]
Calvin Johnson2deb8c92018-03-08 15:30:27 +05301/*
2 * Copyright 2015-2016 Freescale Semiconductor, Inc.
3 * Copyright 2017 NXP
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
8#ifndef _BMU_H_
9#define _BMU_H_
10
11#define BMU_VERSION 0x000
12#define BMU_CTRL 0x004
13#define BMU_UCAST_CONFIG 0x008
14#define BMU_UCAST_BASE_ADDR 0x00c
15#define BMU_BUF_SIZE 0x010
16#define BMU_BUF_CNT 0x014
17#define BMU_THRES 0x018
18#define BMU_INT_SRC 0x020
19#define BMU_INT_ENABLE 0x024
20#define BMU_ALLOC_CTRL 0x030
21#define BMU_FREE_CTRL 0x034
22#define BMU_FREE_ERR_ADDR 0x038
23#define BMU_CURR_BUF_CNT 0x03c
24#define BMU_MCAST_CNT 0x040
25#define BMU_MCAST_ALLOC_CTRL 0x044
26#define BMU_REM_BUF_CNT 0x048
27#define BMU_LOW_WATERMARK 0x050
28#define BMU_HIGH_WATERMARK 0x054
29#define BMU_INT_MEM_ACCESS 0x100
30
31struct bmu_cfg {
32 u32 baseaddr;
33 u32 count;
34 u32 size;
35};
36
37#define BMU1_BUF_SIZE LMEM_BUF_SIZE_LN2
38#define BMU2_BUF_SIZE DDR_BUF_SIZE_LN2
39
40#endif /* _BMU_H_ */