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Sergei Poselenovf2bf96c2008-04-30 11:42:50 +02001/*
2 * (C) Copyright 2008
3 * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com.
4 *
5 * Wolfgang Denk <wd@denx.de>
6 * Copyright 2004 Freescale Semiconductor.
7 * (C) Copyright 2002,2003 Motorola,Inc.
8 * Xianghua Xiao <X.Xiao@motorola.com>
9 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +020010 * SPDX-License-Identifier: GPL-2.0+
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +020011 */
12
13/*
14 * Socrates
15 */
16
17#ifndef __CONFIG_H
18#define __CONFIG_H
19
u-boot@bugs.denx.def0421ec2008-09-11 15:40:01 +020020/* new uImage format support */
21#define CONFIG_FIT 1
22#define CONFIG_OF_LIBFDT 1
23#define CONFIG_FIT_VERBOSE 1 /* enable fit_format_{error,warning}() */
24
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +020025/* High Level Configuration Options */
26#define CONFIG_BOOKE 1 /* BOOKE */
27#define CONFIG_E500 1 /* BOOKE e500 family */
28#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41 */
29#define CONFIG_MPC8544 1
30#define CONFIG_SOCRATES 1
31
Wolfgang Denk291ba1b2010-10-06 09:05:45 +020032#define CONFIG_SYS_TEXT_BASE 0xfff80000
33
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +020034#define CONFIG_PCI
Gabor Juhosb4458732013-05-30 07:06:12 +000035#define CONFIG_PCI_INDIRECT_BRIDGE
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +020036
37#define CONFIG_TSEC_ENET /* tsec ethernet support */
38
39#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
Detlev Zundel0244f672008-08-15 15:42:12 +020040#define CONFIG_BOARD_EARLY_INIT_R 1 /* Call board_early_init_r */
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +020041
42#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
43
44/*
45 * Only possible on E500 Version 2 or newer cores.
46 */
47#define CONFIG_ENABLE_36BIT_PHYS 1
48
49/*
50 * sysclk for MPC85xx
51 *
52 * Two valid values are:
53 * 33000000
54 * 66000000
55 *
56 * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
57 * is likely the desired value here, so that is now the default.
58 * The board, however, can run at 66MHz. In any event, this value
59 * must match the settings of some switches. Details can be found
60 * in the README.mpc85xxads.
61 */
62
63#ifndef CONFIG_SYS_CLK_FREQ
64#define CONFIG_SYS_CLK_FREQ 66666666
65#endif
66
67/*
68 * These can be toggled for performance analysis, otherwise use default.
69 */
70#define CONFIG_L2_CACHE /* toggle L2 cache */
71#define CONFIG_BTB /* toggle branch predition */
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +020072
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020073#define CONFIG_SYS_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +020074
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020075#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
76#define CONFIG_SYS_MEMTEST_START 0x00400000
77#define CONFIG_SYS_MEMTEST_END 0x00C00000
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +020078
Timur Tabid8f341c2011-08-04 18:03:41 -050079#define CONFIG_SYS_CCSRBAR 0xE0000000
80#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +020081
Kumar Gala01135a82008-08-26 22:56:56 -050082/* DDR Setup */
83#define CONFIG_FSL_DDR2
84#undef CONFIG_FSL_DDR_INTERACTIVE
85#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
86#define CONFIG_DDR_SPD
87
88#undef CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
89#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
90
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020091#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
92#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
Kumar Gala01135a82008-08-26 22:56:56 -050093#define CONFIG_VERY_BIG_RAM
94
95#define CONFIG_NUM_DDR_CONTROLLERS 1
96#define CONFIG_DIMM_SLOTS_PER_CTLR 1
97#define CONFIG_CHIP_SELECTS_PER_CTRL 2
98
99/* I2C addresses of SPD EEPROMs */
Anatolij Gustschin2c04bc32008-09-17 11:45:51 +0200100#define SPD_EEPROM_ADDRESS 0x50 /* CTLR 0 DIMM 0 */
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +0200101
102#define CONFIG_DDR_DEFAULT_CL 30 /* CAS latency 3 */
103
104/* Hardcoded values, to use instead of SPD */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200105#define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f
106#define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102
107#define CONFIG_SYS_DDR_TIMING_0 0x00260802
108#define CONFIG_SYS_DDR_TIMING_1 0x3935D322
109#define CONFIG_SYS_DDR_TIMING_2 0x14904CC8
110#define CONFIG_SYS_DDR_MODE 0x00480432
111#define CONFIG_SYS_DDR_INTERVAL 0x030C0100
112#define CONFIG_SYS_DDR_CONFIG_2 0x04400000
113#define CONFIG_SYS_DDR_CONFIG 0xC3008000
114#define CONFIG_SYS_DDR_CLK_CONTROL 0x03800000
115#define CONFIG_SYS_SDRAM_SIZE 256 /* in Megs */
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +0200116
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +0200117/*
118 * Flash on the LocalBus
119 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200120#define CONFIG_SYS_LBC_CACHE_BASE 0xf0000000 /* Localbus cacheable */
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +0200121
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200122#define CONFIG_SYS_FLASH0 0xFE000000
123#define CONFIG_SYS_FLASH1 0xFC000000
124#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH1, CONFIG_SYS_FLASH0 }
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +0200125
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200126#define CONFIG_SYS_LBC_FLASH_BASE CONFIG_SYS_FLASH1 /* Localbus flash start */
127#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_LBC_FLASH_BASE /* start of FLASH */
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +0200128
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200129#define CONFIG_SYS_BR0_PRELIM 0xfe001001 /* port size 16bit */
130#define CONFIG_SYS_OR0_PRELIM 0xfe000030 /* 32MB Flash */
131#define CONFIG_SYS_BR1_PRELIM 0xfc001001 /* port size 16bit */
132#define CONFIG_SYS_OR1_PRELIM 0xfe000030 /* 32MB Flash */
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +0200133
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200134#define CONFIG_SYS_FLASH_CFI /* flash is CFI compat. */
Jean-Christophe PLAGNIOL-VILLARD8d94c232008-08-13 01:40:42 +0200135#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver*/
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +0200136
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200137#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
138#define CONFIG_SYS_MAX_FLASH_SECT 256 /* sectors per device */
139#undef CONFIG_SYS_FLASH_CHECKSUM
140#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
141#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +0200142
Wolfgang Denk0708bc62010-10-07 21:51:12 +0200143#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +0200144
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200145#define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */
146#define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
147#define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
148#define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer presc.*/
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +0200149
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200150#define CONFIG_SYS_INIT_RAM_LOCK 1
151#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
Wolfgang Denk1c2e98e2010-10-26 13:32:32 +0200152#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size used area in RAM*/
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +0200153
Wolfgang Denk0191e472010-10-26 14:34:52 +0200154#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200155#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +0200156
Detlev Zundel2aba8a12010-04-14 11:32:20 +0200157#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384KiB for Mon */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200158#define CONFIG_SYS_MALLOC_LEN (4 << 20) /* Reserve 4 MB for malloc */
Detlev Zundel0244f672008-08-15 15:42:12 +0200159
160/* FPGA and NAND */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200161#define CONFIG_SYS_FPGA_BASE 0xc0000000
162#define CONFIG_SYS_FPGA_SIZE 0x00100000 /* 1 MB */
163#define CONFIG_SYS_HMI_BASE 0xc0010000
164#define CONFIG_SYS_BR3_PRELIM 0xc0001881 /* UPMA, 32-bit */
165#define CONFIG_SYS_OR3_PRELIM 0xfff00000 /* 1 MB */
Detlev Zundel0244f672008-08-15 15:42:12 +0200166
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200167#define CONFIG_SYS_NAND_BASE (CONFIG_SYS_FPGA_BASE + 0x70)
168#define CONFIG_SYS_MAX_NAND_DEVICE 1
Detlev Zundel0244f672008-08-15 15:42:12 +0200169#define CONFIG_CMD_NAND
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +0200170
Anatolij Gustschine6f5c912008-08-15 15:42:13 +0200171/* LIME GDC */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200172#define CONFIG_SYS_LIME_BASE 0xc8000000
173#define CONFIG_SYS_LIME_SIZE 0x04000000 /* 64 MB */
174#define CONFIG_SYS_BR2_PRELIM 0xc80018a1 /* UPMB, 32-bit */
175#define CONFIG_SYS_OR2_PRELIM 0xfc000000 /* 64 MB */
Anatolij Gustschine6f5c912008-08-15 15:42:13 +0200176
177#define CONFIG_VIDEO
178#define CONFIG_VIDEO_MB862xx
Anatolij Gustschine7e44a02009-10-23 12:03:14 +0200179#define CONFIG_VIDEO_MB862xx_ACCEL
Anatolij Gustschine6f5c912008-08-15 15:42:13 +0200180#define CONFIG_CFB_CONSOLE
181#define CONFIG_VIDEO_LOGO
182#define CONFIG_VIDEO_BMP_LOGO
183#define CONFIG_CONSOLE_EXTRA_INFO
184#define VIDEO_FB_16BPP_PIXEL_SWAP
Wolfgang Grandeggere1b05842009-10-23 12:03:15 +0200185#define VIDEO_FB_16BPP_WORD_SWAP
Anatolij Gustschine6f5c912008-08-15 15:42:13 +0200186#define CONFIG_VGA_AS_SINGLE_DEVICE
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200187#define CONFIG_SYS_CONSOLE_IS_IN_ENV
Anatolij Gustschine6f5c912008-08-15 15:42:13 +0200188#define CONFIG_VIDEO_SW_CURSOR
189#define CONFIG_SPLASH_SCREEN
190#define CONFIG_VIDEO_BMP_GZIP
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200191#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20) /* decompressed img */
Anatolij Gustschine6f5c912008-08-15 15:42:13 +0200192
Wolfgang Grandeggerb890f9e2009-10-23 12:03:13 +0200193/* SDRAM Clock frequency, 100MHz (0x0000) or 133MHz (0x10000) */
194#define CONFIG_SYS_MB862xx_CCF 0x10000
195/* SDRAM parameter */
196#define CONFIG_SYS_MB862xx_MMR 0x4157BA63
197
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +0200198/* Serial Port */
199
200#define CONFIG_CONS_INDEX 1
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200201#define CONFIG_SYS_NS16550
202#define CONFIG_SYS_NS16550_SERIAL
203#define CONFIG_SYS_NS16550_REG_SIZE 1
204#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +0200205
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200206#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
207#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +0200208
209#define CONFIG_BAUDRATE 115200
210
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200211#define CONFIG_SYS_BAUDRATE_TABLE \
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +0200212 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
213
214#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
Kim Phillipsf7758c12010-07-14 19:47:18 -0500215#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200216#define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +0200217
218
219/*
220 * I2C
221 */
Heiko Schocherf2850742012-10-24 13:48:22 +0200222#define CONFIG_SYS_I2C
223#define CONFIG_SYS_I2C_FSL
224#define CONFIG_SYS_FSL_I2C_SPEED 102124
225#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
226#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
227#define CONFIG_SYS_FSL_I2C2_SPEED 102124
228#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
229#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
Detlev Zundel0244f672008-08-15 15:42:12 +0200230
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +0200231/* I2C RTC */
Sergei Poselenov09842c52008-05-07 15:10:49 +0200232#define CONFIG_RTC_RX8025 /* Use Epson rx8025 rtc via i2c */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200233#define CONFIG_SYS_I2C_RTC_ADDR 0x32 /* at address 0x32 */
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +0200234
Anatolij Gustschine6f5c912008-08-15 15:42:13 +0200235/* I2C W83782G HW-Monitoring IC */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200236#define CONFIG_SYS_I2C_W83782G_ADDR 0x28 /* W83782G address */
Anatolij Gustschine6f5c912008-08-15 15:42:13 +0200237
Sergei Poselenov92cdc442008-05-27 10:36:07 +0200238/* I2C temp sensor */
239/* Socrates uses Maxim's DS75, which is compatible with LM75 */
240#define CONFIG_DTT_LM75 1
241#define CONFIG_DTT_SENSORS {4} /* Sensor addresses */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200242#define CONFIG_SYS_DTT_MAX_TEMP 125
243#define CONFIG_SYS_DTT_LOW_TEMP -55
244#define CONFIG_SYS_DTT_HYSTERESIS 3
245#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
Sergei Poselenov92cdc442008-05-27 10:36:07 +0200246
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +0200247/*
248 * General PCI
249 * Memory space is mapped 1-1.
250 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200251#define CONFIG_SYS_PCI_PHYS 0x80000000 /* 1G PCI TLB */
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +0200252
Sergei Poselenove13be1a2008-05-27 13:47:00 +0200253/* PCI is clocked by the external source at 33 MHz */
254#define CONFIG_PCI_CLK_FREQ 33000000
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200255#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
256#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
257#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
258#define CONFIG_SYS_PCI1_IO_BASE 0xE2000000
259#define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE
260#define CONFIG_SYS_PCI1_IO_SIZE 0x01000000 /* 16M */
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +0200261
262#if defined(CONFIG_PCI)
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +0200263#define CONFIG_PCI_PNP /* do pci plug-and-play */
Sergei Poselenov18343da2008-06-06 15:42:39 +0200264#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +0200265#endif /* CONFIG_PCI */
266
267
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +0200268#define CONFIG_MII 1 /* MII PHY management */
269#define CONFIG_TSEC1 1
270#define CONFIG_TSEC1_NAME "TSEC0"
Sergei Poselenov6be57752008-05-08 17:46:23 +0200271#define CONFIG_TSEC3 1
272#define CONFIG_TSEC3_NAME "TSEC1"
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +0200273#undef CONFIG_MPC85XX_FEC
274
275#define TSEC1_PHY_ADDR 0
Sergei Poselenov6be57752008-05-08 17:46:23 +0200276#define TSEC3_PHY_ADDR 1
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +0200277
278#define TSEC1_PHYIDX 0
Sergei Poselenov6be57752008-05-08 17:46:23 +0200279#define TSEC3_PHYIDX 0
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +0200280#define TSEC1_FLAGS TSEC_GIGABIT
Sergei Poselenov6be57752008-05-08 17:46:23 +0200281#define TSEC3_FLAGS TSEC_GIGABIT
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +0200282
Sergei Poselenov6be57752008-05-08 17:46:23 +0200283/* Options are: TSEC[0,1] */
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +0200284#define CONFIG_ETHPRIME "TSEC0"
285#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
286
Sergei Poselenov09842c52008-05-07 15:10:49 +0200287#define CONFIG_HAS_ETH0
288#define CONFIG_HAS_ETH1
289
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +0200290/*
291 * Environment
292 */
Jean-Christophe PLAGNIOL-VILLARD53db4cd2008-09-10 22:48:04 +0200293#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +0200294#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200295#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +0200296#define CONFIG_ENV_SIZE 0x4000
297#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
298#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +0200299
300#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200301#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +0200302
303#define CONFIG_TIMESTAMP /* Print image info with ts */
304
305
306/*
307 * BOOTP options
308 */
309#define CONFIG_BOOTP_BOOTFILESIZE
310#define CONFIG_BOOTP_BOOTPATH
311#define CONFIG_BOOTP_GATEWAY
312#define CONFIG_BOOTP_HOSTNAME
313
314
315/*
316 * Command line configuration.
317 */
318#include <config_cmd_default.h>
319
Detlev Zundel2aba8a12010-04-14 11:32:20 +0200320#define CONFIG_CMD_BMP
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +0200321#define CONFIG_CMD_DATE
322#define CONFIG_CMD_DHCP
Sergei Poselenov92cdc442008-05-27 10:36:07 +0200323#define CONFIG_CMD_DTT
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +0200324#undef CONFIG_CMD_EEPROM
Detlev Zundel2aba8a12010-04-14 11:32:20 +0200325#define CONFIG_CMD_EXT2 /* EXT2 Support */
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +0200326#define CONFIG_CMD_I2C
Detlev Zundel0244f672008-08-15 15:42:12 +0200327#define CONFIG_CMD_SDRAM
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +0200328#define CONFIG_CMD_MII
Detlev Zundel2aba8a12010-04-14 11:32:20 +0200329#undef CONFIG_CMD_NFS
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +0200330#define CONFIG_CMD_PING
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +0200331#define CONFIG_CMD_SNTP
Sergei Poselenoveeaaa612008-05-27 11:49:13 +0200332#define CONFIG_CMD_USB
Becky Bruceee888da2010-06-17 11:37:25 -0500333#define CONFIG_CMD_REGINFO
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +0200334
335#if defined(CONFIG_PCI)
336 #define CONFIG_CMD_PCI
337#endif
338
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +0200339#undef CONFIG_WATCHDOG /* watchdog disabled */
340
341/*
342 * Miscellaneous configurable options
343 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200344#define CONFIG_SYS_LONGHELP /* undef to save memory */
345#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
346#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +0200347
348#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200349 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +0200350#else
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200351 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +0200352#endif
353
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200354#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buf Size */
355#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
356#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
357#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +0200358
359/*
360 * For booting Linux, the board info and command line data
361 * have to be in the first 8 MB of memory, since this is
362 * the maximum mapped by the Linux kernel during initialization.
363 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200364#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +0200365
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +0200366#if defined(CONFIG_CMD_KGDB)
367#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port*/
368#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
369#endif
370
371
372#define CONFIG_LOADADDR 200000 /* default addr for tftp & bootm*/
373
Detlev Zundel0244f672008-08-15 15:42:12 +0200374#define CONFIG_BOOTDELAY 1 /* -1 disables auto-boot */
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +0200375
376#define CONFIG_PREBOOT "echo;" \
Detlev Zundel0244f672008-08-15 15:42:12 +0200377 "echo Welcome on the ABB Socrates Board;" \
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +0200378 "echo"
379
380#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
381
382#define CONFIG_EXTRA_ENV_SETTINGS \
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +0200383 "netdev=eth0\0" \
384 "consdev=ttyS0\0" \
Detlev Zundel0244f672008-08-15 15:42:12 +0200385 "uboot_file=/home/tftp/syscon3/u-boot.bin\0" \
386 "bootfile=/home/tftp/syscon3/uImage\0" \
387 "fdt_file=/home/tftp/syscon3/socrates.dtb\0" \
388 "initrd_file=/home/tftp/syscon3/uinitrd.gz\0" \
389 "uboot_addr=FFFA0000\0" \
390 "kernel_addr=FE000000\0" \
391 "fdt_addr=FE1E0000\0" \
392 "ramdisk_addr=FE200000\0" \
393 "fdt_addr_r=B00000\0" \
394 "kernel_addr_r=200000\0" \
395 "ramdisk_addr_r=400000\0" \
396 "rootpath=/opt/eldk/ppc_85xxDP\0" \
397 "ramargs=setenv bootargs root=/dev/ram rw\0" \
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +0200398 "nfsargs=setenv bootargs root=/dev/nfs rw " \
399 "nfsroot=$serverip:$rootpath\0" \
Detlev Zundel0244f672008-08-15 15:42:12 +0200400 "addcons=setenv bootargs $bootargs " \
401 "console=$consdev,$baudrate\0" \
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +0200402 "addip=setenv bootargs $bootargs " \
403 "ip=$ipaddr:$serverip:$gatewayip:$netmask" \
404 ":$hostname:$netdev:off panic=1\0" \
Detlev Zundel0244f672008-08-15 15:42:12 +0200405 "boot_nor=run ramargs addcons;" \
Sergei Poselenov09842c52008-05-07 15:10:49 +0200406 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
Sergei Poselenov09842c52008-05-07 15:10:49 +0200407 "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \
408 "tftp ${fdt_addr_r} ${fdt_file}; " \
409 "run nfsargs addip addcons;" \
410 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
Detlev Zundel0244f672008-08-15 15:42:12 +0200411 "update_uboot=tftp 100000 ${uboot_file};" \
412 "protect off fffa0000 ffffffff;" \
413 "era fffa0000 ffffffff;" \
414 "cp.b 100000 fffa0000 ${filesize};" \
415 "setenv filesize;saveenv\0" \
416 "update_kernel=tftp 100000 ${bootfile};" \
417 "era fe000000 fe1dffff;" \
418 "cp.b 100000 fe000000 ${filesize};" \
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +0200419 "setenv filesize;saveenv\0" \
Detlev Zundel0244f672008-08-15 15:42:12 +0200420 "update_fdt=tftp 100000 ${fdt_file};" \
421 "era fe1e0000 fe1fffff;" \
422 "cp.b 100000 fe1e0000 ${filesize};" \
423 "setenv filesize;saveenv\0" \
424 "update_initrd=tftp 100000 ${initrd_file};" \
425 "era fe200000 fe9fffff;" \
426 "cp.b 100000 fe200000 ${filesize};" \
427 "setenv filesize;saveenv\0" \
428 "clean_data=era fea00000 fff5ffff\0" \
429 "usbargs=setenv bootargs root=/dev/sda1 rw\0" \
430 "load_usb=usb start;" \
431 "ext2load usb 0:1 ${kernel_addr_r} /boot/uImage\0" \
432 "boot_usb=run load_usb usbargs addcons;" \
433 "bootm ${kernel_addr_r} - ${fdt_addr};" \
434 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +0200435 ""
Detlev Zundel0244f672008-08-15 15:42:12 +0200436#define CONFIG_BOOTCOMMAND "run boot_nor"
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +0200437
Sergei Poselenov09842c52008-05-07 15:10:49 +0200438/* pass open firmware flat tree */
439#define CONFIG_OF_LIBFDT 1
440#define CONFIG_OF_BOARD_SETUP 1
441
Sergei Poselenoveeaaa612008-05-27 11:49:13 +0200442/* USB support */
443#define CONFIG_USB_OHCI_NEW 1
444#define CONFIG_PCI_OHCI 1
445#define CONFIG_PCI_OHCI_DEVNO 3 /* Number in PCI list */
Yuri Tikhonov11af42c2008-09-04 11:19:05 +0200446#define CONFIG_PCI_EHCI_DEVNO (CONFIG_PCI_OHCI_DEVNO / 2)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200447#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
448#define CONFIG_SYS_USB_OHCI_SLOT_NAME "ohci_pci"
449#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1
Sergei Poselenoveeaaa612008-05-27 11:49:13 +0200450#define CONFIG_DOS_PARTITION 1
451#define CONFIG_USB_STORAGE 1
452
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +0200453#endif /* __CONFIG_H */