blob: 3f586fbbc13f522eaee524b8d52c8101328604e5 [file] [log] [blame]
Heiko Schocher3ec43662006-12-21 17:17:02 +01001/*
2 * (C) Copyright 2006
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
Heiko Schocher3ec43662006-12-21 17:17:02 +01006 */
7
8/*
9 * board/config.h - configuration options, board specific
10 */
11
12#ifndef __CONFIG_H
13#define __CONFIG_H
14
15/*
16 * High Level Configuration Options
17 * (easy to change)
18 */
19
20#define CONFIG_MPC8260 1 /* This is a MPC8260 CPU */
21#define CONFIG_MPC8272_FAMILY 1
22#define CONFIG_TQM8272 1
23
Wolfgang Denk291ba1b2010-10-06 09:05:45 +020024#define CONFIG_SYS_TEXT_BASE 0x40000000
25
Heiko Schocher3ec43662006-12-21 17:17:02 +010026#define CONFIG_GET_CPU_STR_F 1 /* Get the CPU ID STR */
Wolfgang Denk52e9f302006-12-24 01:42:57 +010027#define CONFIG_BOARD_GET_CPU_CLK_F 1 /* Get the CLKIN from board fct */
28
Heiko Schocher3ec43662006-12-21 17:17:02 +010029#define STK82xx_150 1 /* on a STK82xx.150 */
30
31#define CONFIG_CPM2 1 /* Has a CPM2 */
32
33#define CONFIG_82xx_CONS_SMC1 1 /* console on SMC1 */
34
35#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
36
37#define CONFIG_BOARD_EARLY_INIT_R 1
38
39#if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC)
40#define CONFIG_BAUDRATE 230400
41#else
42#define CONFIG_BAUDRATE 115200
43#endif
44
Wolfgang Denk1baed662008-03-03 12:16:44 +010045#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
Heiko Schocher3ec43662006-12-21 17:17:02 +010046
47#undef CONFIG_BOOTARGS
48
49#define CONFIG_EXTRA_ENV_SETTINGS \
50 "netdev=eth0\0" \
51 "consdev=ttyCPM0\0" \
52 "nfsargs=setenv bootargs root=/dev/nfs rw " \
53 "nfsroot=${serverip}:${rootpath}\0" \
54 "ramargs=setenv bootargs root=/dev/ram rw\0" \
55 "hostname=tqm8272\0" \
56 "addip=setenv bootargs ${bootargs} " \
57 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
58 ":${hostname}:${netdev}:off panic=1\0" \
59 "addcons=setenv bootargs ${bootargs} " \
Wolfgang Denk52e9f302006-12-24 01:42:57 +010060 "console=$(consdev),$(baudrate)\0" \
61 "flash_nfs=run nfsargs addip addcons;" \
Heiko Schocher3ec43662006-12-21 17:17:02 +010062 "bootm ${kernel_addr}\0" \
Wolfgang Denk52e9f302006-12-24 01:42:57 +010063 "flash_self=run ramargs addip addcons;" \
Heiko Schocher3ec43662006-12-21 17:17:02 +010064 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
65 "net_nfs=tftp 300000 ${bootfile};" \
Wolfgang Denk52e9f302006-12-24 01:42:57 +010066 "run nfsargs addip addcons;bootm\0" \
Heiko Schocher3ec43662006-12-21 17:17:02 +010067 "rootpath=/opt/eldk/ppc_82xx\0" \
68 "bootfile=/tftpboot/tqm8272/uImage\0" \
69 "kernel_addr=40080000\0" \
70 "ramdisk_addr=40100000\0" \
71 "load=tftp 300000 /tftpboot/tqm8272/u-boot.bin\0" \
72 "update=protect off 40000000 4003ffff;era 40000000 4003ffff;" \
73 "cp.b 300000 40000000 40000;" \
74 "setenv filesize;saveenv\0" \
Wolfgang Denk52e9f302006-12-24 01:42:57 +010075 "cphwib=cp.b 4003fc00 33fc00 400\0" \
Detlev Zundel406e5782008-03-06 16:45:53 +010076 "upd=run load cphwib update\0" \
Heiko Schocher3ec43662006-12-21 17:17:02 +010077 ""
78#define CONFIG_BOOTCOMMAND "run flash_self"
79
80#define CONFIG_I2C 1
81
82#if CONFIG_I2C
83/* enable I2C and select the hardware/software driver */
Heiko Schocher479a4cf2013-01-29 08:53:15 +010084#define CONFIG_SYS_I2C
85#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
86#define CONFIG_SYS_I2C_SOFT_SPEED 400000
87#define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F
Heiko Schocher3ec43662006-12-21 17:17:02 +010088/*
89 * Software (bit-bang) I2C driver configuration
90 */
91#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */
92#define I2C_ACTIVE (iop->pdir |= 0x00010000)
93#define I2C_TRISTATE (iop->pdir &= ~0x00010000)
94#define I2C_READ ((iop->pdat & 0x00010000) != 0)
95#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \
96 else iop->pdat &= ~0x00010000
97#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \
98 else iop->pdat &= ~0x00020000
99#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
100
101#define CONFIG_I2C_X
102
103/* EEPROM */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200104#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
105#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
106#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
107#define CONFIG_SYS_I2C_MULTI_EEPROMS 1 /* more than one eeprom */
Heiko Schocher3ec43662006-12-21 17:17:02 +0100108
109/* I2C RTC */
110#define CONFIG_RTC_DS1337 /* Use ds1337 rtc via i2c */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200111#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
Heiko Schocher3ec43662006-12-21 17:17:02 +0100112
113/* I2C SYSMON (LM75) */
114#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */
115#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200116#define CONFIG_SYS_DTT_MAX_TEMP 70
117#define CONFIG_SYS_DTT_LOW_TEMP -30
118#define CONFIG_SYS_DTT_HYSTERESIS 3
Heiko Schocher3ec43662006-12-21 17:17:02 +0100119
120#else
Heiko Schocher479a4cf2013-01-29 08:53:15 +0100121#undef CONFIG_SYS_I2C
Heiko Schocher3ec43662006-12-21 17:17:02 +0100122#undef CONFIG_HARD_I2C
Heiko Schocher479a4cf2013-01-29 08:53:15 +0100123#undef CONFIG_SYS_I2C_SOFT
Heiko Schocher3ec43662006-12-21 17:17:02 +0100124#endif
125
126/*
127 * select serial console configuration
128 *
129 * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
130 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
131 * for SCC).
132 *
133 * if CONFIG_CONS_NONE is defined, then the serial console routines must
134 * defined elsewhere (for example, on the cogent platform, there are serial
135 * ports on the motherboard which are used for the serial console - see
136 * cogent/cma101/serial.[ch]).
137 */
138#define CONFIG_CONS_ON_SMC /* define if console on SMC */
139#undef CONFIG_CONS_ON_SCC /* define if console on SCC */
140#undef CONFIG_CONS_NONE /* define if console on something else*/
141#ifdef CONFIG_82xx_CONS_SMC1
142#define CONFIG_CONS_INDEX 1 /* which serial channel for console */
143#endif
144#ifdef CONFIG_82xx_CONS_SMC2
145#define CONFIG_CONS_INDEX 2 /* which serial channel for console */
146#endif
147
148#undef CONFIG_CONS_USE_EXTC /* SMC/SCC use ext clock not brg_clk */
149#define CONFIG_CONS_EXTC_RATE 3686400 /* SMC/SCC ext clk rate in Hz */
150#define CONFIG_CONS_EXTC_PINSEL 0 /* pin select 0=CLK3/CLK9 */
151
152/*
153 * select ethernet configuration
154 *
155 * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
156 * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
157 * for FCC)
158 *
159 * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
Jon Loeliger2517d972007-07-09 17:15:49 -0500160 * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
Heiko Schocher3ec43662006-12-21 17:17:02 +0100161 *
162 * (On TQM8272 either SCC1 or FCC2 may be chosen: SCC1 is hardwired to the
163 * X.29 connector, and FCC2 is hardwired to the X.1 connector)
164 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200165#define CONFIG_SYS_FCC_ETHERNET
Heiko Schocher3ec43662006-12-21 17:17:02 +0100166
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200167#if defined(CONFIG_SYS_FCC_ETHERNET)
Heiko Schocher3ec43662006-12-21 17:17:02 +0100168#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */
169#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */
170#undef CONFIG_ETHER_NONE /* define if ether on something else */
171#define CONFIG_ETHER_INDEX 2 /* which SCC/FCC channel for ethernet */
172#else
173#define CONFIG_ETHER_ON_SCC /* define if ether on SCC */
174#undef CONFIG_ETHER_ON_FCC /* define if ether on FCC */
175#undef CONFIG_ETHER_NONE /* define if ether on something else */
176#define CONFIG_ETHER_INDEX 1 /* which SCC/FCC channel for ethernet */
177#endif
178
179#if defined(CONFIG_ETHER_ON_SCC) && (CONFIG_ETHER_INDEX == 1)
180
181/*
182 * - RX clk is CLK11
183 * - TX clk is CLK12
184 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200185# define CONFIG_SYS_CMXSCR_VALUE (CMXSCR_RS1CS_CLK11 | CMXSCR_TS1CS_CLK12)
Heiko Schocher3ec43662006-12-21 17:17:02 +0100186
187#elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2)
188
189/*
190 * - Rx-CLK is CLK13
191 * - Tx-CLK is CLK14
192 * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
193 * - Enable Full Duplex in FSMR
194 */
Mike Frysinger109de972011-10-17 05:38:58 +0000195# define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
196# define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200197# define CONFIG_SYS_CPMFCR_RAMTYPE 0
198# define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB)
Heiko Schocher3ec43662006-12-21 17:17:02 +0100199
200#endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */
201
202#define CONFIG_MII /* MII PHY management */
203#define CONFIG_BITBANGMII /* bit-bang MII PHY management */
204/*
205 * GPIO pins used for bit-banged MII communications
206 */
207#define MDIO_PORT 2 /* Port C */
Luigi 'Comio' Mantellini25e30722009-10-10 12:42:22 +0200208#define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \
209 (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
210#define MDC_DECLARE MDIO_DECLARE
Heiko Schocher3ec43662006-12-21 17:17:02 +0100211
212#if STK82xx_150
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200213#define CONFIG_SYS_MDIO_PIN 0x00008000 /* PC16 */
214#define CONFIG_SYS_MDC_PIN 0x00004000 /* PC17 */
Heiko Schocher3ec43662006-12-21 17:17:02 +0100215#endif
216
217#if STK82xx_100
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200218#define CONFIG_SYS_MDIO_PIN 0x00000002 /* PC30 */
219#define CONFIG_SYS_MDC_PIN 0x00000001 /* PC31 */
Heiko Schocher3ec43662006-12-21 17:17:02 +0100220#endif
221
222#if 1
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200223#define MDIO_ACTIVE (iop->pdir |= CONFIG_SYS_MDIO_PIN)
224#define MDIO_TRISTATE (iop->pdir &= ~CONFIG_SYS_MDIO_PIN)
225#define MDIO_READ ((iop->pdat & CONFIG_SYS_MDIO_PIN) != 0)
Heiko Schocher3ec43662006-12-21 17:17:02 +0100226
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200227#define MDIO(bit) if(bit) iop->pdat |= CONFIG_SYS_MDIO_PIN; \
228 else iop->pdat &= ~CONFIG_SYS_MDIO_PIN
Heiko Schocher3ec43662006-12-21 17:17:02 +0100229
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200230#define MDC(bit) if(bit) iop->pdat |= CONFIG_SYS_MDC_PIN; \
231 else iop->pdat &= ~CONFIG_SYS_MDC_PIN
Heiko Schocher3ec43662006-12-21 17:17:02 +0100232#else
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200233#define MDIO_ACTIVE ({unsigned long tmp; tmp = iop->pdir; tmp |= CONFIG_SYS_MDIO_PIN; iop->pdir = tmp;})
234#define MDIO_TRISTATE ({unsigned long tmp; tmp = iop->pdir; tmp &= ~CONFIG_SYS_MDIO_PIN; iop->pdir = tmp;})
235#define MDIO_READ ((iop->pdat & CONFIG_SYS_MDIO_PIN) != 0)
Heiko Schocher3ec43662006-12-21 17:17:02 +0100236
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200237#define MDIO(bit) if(bit) {unsigned long tmp; tmp = iop->pdat; tmp |= CONFIG_SYS_MDIO_PIN; iop->pdat = tmp;}\
238 else {unsigned long tmp; tmp = iop->pdat; tmp &= ~CONFIG_SYS_MDIO_PIN; iop->pdat = tmp;}
Heiko Schocher3ec43662006-12-21 17:17:02 +0100239
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200240#define MDC(bit) if(bit) {unsigned long tmp; tmp = iop->pdat; tmp |= CONFIG_SYS_MDC_PIN; iop->pdat = tmp;}\
241 else {unsigned long tmp; tmp = iop->pdat; tmp &= ~CONFIG_SYS_MDC_PIN; iop->pdat = tmp;}
Heiko Schocher3ec43662006-12-21 17:17:02 +0100242#endif
243
244#define MIIDELAY udelay(1)
245
246
Heiko Schocher3ec43662006-12-21 17:17:02 +0100247/* system clock rate (CLKIN) - equal to the 60x and local bus speed */
248#define CONFIG_8260_CLKIN 66666666 /* in Hz */
249
250#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200251#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
Heiko Schocher3ec43662006-12-21 17:17:02 +0100252
253#undef CONFIG_WATCHDOG /* watchdog disabled */
254
255#define CONFIG_TIMESTAMP /* Print image info with timestamp */
256
Jon Loeliger530ca672007-07-09 21:38:02 -0500257/*
258 * BOOTP options
259 */
260#define CONFIG_BOOTP_SUBNETMASK
261#define CONFIG_BOOTP_GATEWAY
262#define CONFIG_BOOTP_HOSTNAME
263#define CONFIG_BOOTP_BOOTPATH
264#define CONFIG_BOOTP_BOOTFILESIZE
Heiko Schocher3ec43662006-12-21 17:17:02 +0100265
Heiko Schocher3ec43662006-12-21 17:17:02 +0100266
Jon Loeligeredccb462007-07-04 22:30:50 -0500267/*
268 * Command line configuration.
269 */
270#include <config_cmd_default.h>
271
272#define CONFIG_CMD_I2C
273#define CONFIG_CMD_DHCP
274#define CONFIG_CMD_MII
275#define CONFIG_CMD_NAND
276#define CONFIG_CMD_NFS
277#define CONFIG_CMD_PCI
278#define CONFIG_CMD_PING
279#define CONFIG_CMD_SNTP
280
Jon Loeligerbeb9ff42007-07-10 09:22:23 -0500281#if CONFIG_I2C
282 #define CONFIG_CMD_I2C
283 #define CONFIG_CMD_DATE
284 #define CONFIG_CMD_DTT
285 #define CONFIG_CMD_EEPROM
286#endif
287
Heiko Schocher3ec43662006-12-21 17:17:02 +0100288
289/*
290 * Miscellaneous configurable options
291 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200292#define CONFIG_SYS_LONGHELP /* undef to save memory */
293#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Heiko Schocher3ec43662006-12-21 17:17:02 +0100294
295#if 0
296#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200297#define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */
Heiko Schocher3ec43662006-12-21 17:17:02 +0100298#endif
299
Jon Loeligeredccb462007-07-04 22:30:50 -0500300#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200301#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Heiko Schocher3ec43662006-12-21 17:17:02 +0100302#else
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200303#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Heiko Schocher3ec43662006-12-21 17:17:02 +0100304#endif
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200305#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
306#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
307#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
Heiko Schocher3ec43662006-12-21 17:17:02 +0100308
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200309#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
310#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
Heiko Schocher3ec43662006-12-21 17:17:02 +0100311
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200312#define CONFIG_SYS_LOAD_ADDR 0x300000 /* default load address */
Heiko Schocher3ec43662006-12-21 17:17:02 +0100313
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200314#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
Heiko Schocher3ec43662006-12-21 17:17:02 +0100315
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200316#define CONFIG_SYS_RESET_ADDRESS 0x40000104 /* "bad" address */
Heiko Schocher3ec43662006-12-21 17:17:02 +0100317
318/*
319 * For booting Linux, the board info and command line data
320 * have to be in the first 8 MB of memory, since this is
321 * the maximum mapped by the Linux kernel during initialization.
322 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200323#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
Heiko Schocher3ec43662006-12-21 17:17:02 +0100324
325/*-----------------------------------------------------------------------
326 * CAN stuff
327 *-----------------------------------------------------------------------
328 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200329#define CONFIG_SYS_CAN_BASE 0x51000000
330#define CONFIG_SYS_CAN_SIZE 1
331#define CONFIG_SYS_CAN_BR ((CONFIG_SYS_CAN_BASE & BRx_BA_MSK) |\
Heiko Schocher3ec43662006-12-21 17:17:02 +0100332 BRx_PS_8 |\
333 BRx_MS_UPMC |\
334 BRx_V)
335
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200336#define CONFIG_SYS_CAN_OR (MEG_TO_AM(CONFIG_SYS_CAN_SIZE) |\
Heiko Schocher3ec43662006-12-21 17:17:02 +0100337 ORxU_BI)
338
339
340/* What should the base address of the main FLASH be and how big is
Wolfgang Denk0708bc62010-10-07 21:51:12 +0200341 * it (in MBytes)? This must contain CONFIG_SYS_TEXT_BASE from board/tqm8272/config.mk
Heiko Schocher3ec43662006-12-21 17:17:02 +0100342 * The main FLASH is whichever is connected to *CS0.
343 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200344#define CONFIG_SYS_FLASH0_BASE 0x40000000
345#define CONFIG_SYS_FLASH0_SIZE 32 /* 32 MB */
Heiko Schocher3ec43662006-12-21 17:17:02 +0100346
347/* Flash bank size (for preliminary settings)
348 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200349#define CONFIG_SYS_FLASH_SIZE CONFIG_SYS_FLASH0_SIZE
Heiko Schocher3ec43662006-12-21 17:17:02 +0100350
351/*-----------------------------------------------------------------------
352 * FLASH organization
353 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200354#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
355#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */
Heiko Schocher3ec43662006-12-21 17:17:02 +0100356
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200357#define CONFIG_SYS_FLASH_CFI /* flash is CFI compat. */
Jean-Christophe PLAGNIOL-VILLARD8d94c232008-08-13 01:40:42 +0200358#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver*/
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200359#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector */
360#define CONFIG_SYS_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash*/
Heiko Schocher3ec43662006-12-21 17:17:02 +0100361
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200362#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
363#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
Heiko Schocher3ec43662006-12-21 17:17:02 +0100364
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200365#define CONFIG_SYS_UPDATE_FLASH_SIZE
Heiko Schocher3ec43662006-12-21 17:17:02 +0100366
Jean-Christophe PLAGNIOL-VILLARD53db4cd2008-09-10 22:48:04 +0200367#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200368#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x40000)
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +0200369#define CONFIG_ENV_SIZE 0x20000
370#define CONFIG_ENV_SECT_SIZE 0x20000
371#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SIZE)
372#define CONFIG_ENV_SIZE_REDUND 0x20000
Heiko Schocher3ec43662006-12-21 17:17:02 +0100373
374/* Where is the Hardwareinformation Block (from Monitor Sources) */
375#define MON_RES_LENGTH (0x0003FC00)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200376#define HWIB_INFO_START_ADDR (CONFIG_SYS_FLASH_BASE + MON_RES_LENGTH)
Heiko Schocher3ec43662006-12-21 17:17:02 +0100377#define HWIB_INFO_LEN 512
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200378#define CIB_INFO_START_ADDR (CONFIG_SYS_FLASH_BASE + MON_RES_LENGTH + HWIB_INFO_LEN)
Heiko Schocher3ec43662006-12-21 17:17:02 +0100379#define CIB_INFO_LEN 512
380
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200381#define CONFIG_SYS_HWINFO_OFFSET 0x3fc00 /* offset of HW Info block */
382#define CONFIG_SYS_HWINFO_SIZE 0x00000060 /* size of HW Info block */
383#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
Heiko Schocher3ec43662006-12-21 17:17:02 +0100384
385/*-----------------------------------------------------------------------
386 * NAND-FLASH stuff
387 *-----------------------------------------------------------------------
388 */
Jon Loeligeredccb462007-07-04 22:30:50 -0500389#if defined(CONFIG_CMD_NAND)
Heiko Schocher3ec43662006-12-21 17:17:02 +0100390
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200391#define CONFIG_SYS_NAND_CS_DIST 0x80
392#define CONFIG_SYS_NAND_UPM_WRITE_CMD_OFS 0x20
393#define CONFIG_SYS_NAND_UPM_WRITE_ADDR_OFS 0x40
Heiko Schocher3ec43662006-12-21 17:17:02 +0100394
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200395#define CONFIG_SYS_NAND_BR ((CONFIG_SYS_NAND0_BASE & BRx_BA_MSK) |\
Heiko Schocher3ec43662006-12-21 17:17:02 +0100396 BRx_PS_8 |\
397 BRx_MS_UPMB |\
398 BRx_V)
399
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200400#define CONFIG_SYS_NAND_OR (MEG_TO_AM(CONFIG_SYS_NAND_SIZE) |\
Heiko Schocher3ec43662006-12-21 17:17:02 +0100401 ORxU_BI |\
402 ORxU_EHTR_8IDLE)
403
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200404#define CONFIG_SYS_NAND_SIZE 1
405#define CONFIG_SYS_NAND0_BASE 0x50000000
406#define CONFIG_SYS_NAND1_BASE (CONFIG_SYS_NAND0_BASE + CONFIG_SYS_NAND_CS_DIST)
407#define CONFIG_SYS_NAND2_BASE (CONFIG_SYS_NAND1_BASE + CONFIG_SYS_NAND_CS_DIST)
408#define CONFIG_SYS_NAND3_BASE (CONFIG_SYS_NAND2_BASE + CONFIG_SYS_NAND_CS_DIST)
Heiko Schocher3ec43662006-12-21 17:17:02 +0100409
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200410#define CONFIG_SYS_MAX_NAND_DEVICE 4 /* Max number of NAND devices */
Heiko Schocher3ec43662006-12-21 17:17:02 +0100411
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200412#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND0_BASE, \
413 CONFIG_SYS_NAND1_BASE, \
414 CONFIG_SYS_NAND2_BASE, \
415 CONFIG_SYS_NAND3_BASE, \
Heiko Schocher3ec43662006-12-21 17:17:02 +0100416 }
417
418#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)(adr)) = (__u8)d; } while(0)
419#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)(adr)))
420#define WRITE_NAND_UPM(d, adr, off) do \
421{ \
422 volatile unsigned char *addr = (unsigned char *) (adr + off); \
423 WRITE_NAND(d, addr); \
424} while(0)
425
Jon Loeligerbeb9ff42007-07-10 09:22:23 -0500426#endif /* CONFIG_CMD_NAND */
Heiko Schocher3ec43662006-12-21 17:17:02 +0100427
428#define CONFIG_PCI
429#ifdef CONFIG_PCI
Gabor Juhosb4458732013-05-30 07:06:12 +0000430#define CONFIG_PCI_INDIRECT_BRIDGE
Heiko Schocher3ec43662006-12-21 17:17:02 +0100431#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
432#define CONFIG_PCI_PNP
433#define CONFIG_EEPRO100
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200434#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
Heiko Schocher3ec43662006-12-21 17:17:02 +0100435#define CONFIG_PCI_SCAN_SHOW
436#endif
437
438/*-----------------------------------------------------------------------
439 * Hard Reset Configuration Words
440 *
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200441 * if you change bits in the HRCW, you must also change the CONFIG_SYS_*
Heiko Schocher3ec43662006-12-21 17:17:02 +0100442 * defines for the various registers affected by the HRCW e.g. changing
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200443 * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR.
Heiko Schocher3ec43662006-12-21 17:17:02 +0100444 */
445#if 0
446#define __HRCW__ALL__ (HRCW_CIP | HRCW_ISB111 | HRCW_BMS)
447
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200448# define CONFIG_SYS_HRCW_MASTER (__HRCW__ALL__ | HRCW_MODCK_H0111)
Heiko Schocher3ec43662006-12-21 17:17:02 +0100449#else
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200450#define CONFIG_SYS_HRCW_MASTER (HRCW_BPS11 | HRCW_ISB111 | HRCW_BMS | HRCW_MODCK_H0111)
Heiko Schocher3ec43662006-12-21 17:17:02 +0100451#endif
452
453/* no slaves so just fill with zeros */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200454#define CONFIG_SYS_HRCW_SLAVE1 0
455#define CONFIG_SYS_HRCW_SLAVE2 0
456#define CONFIG_SYS_HRCW_SLAVE3 0
457#define CONFIG_SYS_HRCW_SLAVE4 0
458#define CONFIG_SYS_HRCW_SLAVE5 0
459#define CONFIG_SYS_HRCW_SLAVE6 0
460#define CONFIG_SYS_HRCW_SLAVE7 0
Heiko Schocher3ec43662006-12-21 17:17:02 +0100461
462/*-----------------------------------------------------------------------
463 * Internal Memory Mapped Register
464 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200465#define CONFIG_SYS_IMMR 0xFFF00000
Heiko Schocher3ec43662006-12-21 17:17:02 +0100466
467/*-----------------------------------------------------------------------
468 * Definitions for initial stack pointer and data area (in DPRAM)
469 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200470#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
Wolfgang Denk1c2e98e2010-10-26 13:32:32 +0200471#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in DPRAM */
Wolfgang Denk0191e472010-10-26 14:34:52 +0200472#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200473#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Heiko Schocher3ec43662006-12-21 17:17:02 +0100474
475/*-----------------------------------------------------------------------
476 * Start addresses for the final memory configuration
477 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200478 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
Heiko Schocher3ec43662006-12-21 17:17:02 +0100479 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200480#define CONFIG_SYS_SDRAM_BASE 0x00000000
481#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_FLASH0_BASE
Wolfgang Denk0708bc62010-10-07 21:51:12 +0200482#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200483#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
484#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/
Heiko Schocher3ec43662006-12-21 17:17:02 +0100485
Heiko Schocher3ec43662006-12-21 17:17:02 +0100486/*-----------------------------------------------------------------------
487 * Cache Configuration
488 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200489#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */
Jon Loeligeredccb462007-07-04 22:30:50 -0500490#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200491# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
Heiko Schocher3ec43662006-12-21 17:17:02 +0100492#endif
493
494/*-----------------------------------------------------------------------
495 * HIDx - Hardware Implementation-dependent Registers 2-11
496 *-----------------------------------------------------------------------
497 * HID0 also contains cache control - initially enable both caches and
498 * invalidate contents, then the final state leaves only the instruction
499 * cache enabled. Note that Power-On and Hard reset invalidate the caches,
500 * but Soft reset does not.
501 *
502 * HID1 has only read-only information - nothing to set.
503 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200504#define CONFIG_SYS_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\
Heiko Schocher3ec43662006-12-21 17:17:02 +0100505 HID0_IFEM|HID0_ABE)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200506#define CONFIG_SYS_HID0_FINAL (HID0_IFEM|HID0_ABE)
507#define CONFIG_SYS_HID2 0
Heiko Schocher3ec43662006-12-21 17:17:02 +0100508
509/*-----------------------------------------------------------------------
510 * RMR - Reset Mode Register 5-5
511 *-----------------------------------------------------------------------
512 * turn on Checkstop Reset Enable
513 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200514#define CONFIG_SYS_RMR RMR_CSRE
Heiko Schocher3ec43662006-12-21 17:17:02 +0100515
516/*-----------------------------------------------------------------------
517 * BCR - Bus Configuration 4-25
518 *-----------------------------------------------------------------------
519 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200520#define CONFIG_SYS_BCR_60x (BCR_EBM|BCR_NPQM0|BCR_NPQM2) /* 60x mode */
Heiko Schocher3ec43662006-12-21 17:17:02 +0100521#define BCR_APD01 0x10000000
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200522#define CONFIG_SYS_BCR_SINGLE (BCR_APD01|BCR_ETM) /* 8260 mode */
Heiko Schocher3ec43662006-12-21 17:17:02 +0100523
524/*-----------------------------------------------------------------------
525 * SIUMCR - SIU Module Configuration 4-31
526 *-----------------------------------------------------------------------
527 */
528#if defined(CONFIG_BOARD_GET_CPU_CLK_F)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200529#define CONFIG_SYS_SIUMCR_LOW (SIUMCR_DPPC00)
530#define CONFIG_SYS_SIUMCR_HIGH (SIUMCR_DPPC00 | SIUMCR_ABE)
Heiko Schocher3ec43662006-12-21 17:17:02 +0100531#else
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200532#define CONFIG_SYS_SIUMCR (SIUMCR_DPPC00)
Heiko Schocher3ec43662006-12-21 17:17:02 +0100533#endif
534
535/*-----------------------------------------------------------------------
536 * SYPCR - System Protection Control 4-35
537 * SYPCR can only be written once after reset!
538 *-----------------------------------------------------------------------
539 * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
540 */
541#if defined(CONFIG_WATCHDOG)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200542#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
Heiko Schocher3ec43662006-12-21 17:17:02 +0100543 SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
544#else
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200545#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
Heiko Schocher3ec43662006-12-21 17:17:02 +0100546 SYPCR_SWRI|SYPCR_SWP)
547#endif /* CONFIG_WATCHDOG */
548
549/*-----------------------------------------------------------------------
550 * TMCNTSC - Time Counter Status and Control 4-40
551 *-----------------------------------------------------------------------
552 * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
553 * and enable Time Counter
554 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200555#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
Heiko Schocher3ec43662006-12-21 17:17:02 +0100556
557/*-----------------------------------------------------------------------
558 * PISCR - Periodic Interrupt Status and Control 4-42
559 *-----------------------------------------------------------------------
560 * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
561 * Periodic timer
562 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200563#define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
Heiko Schocher3ec43662006-12-21 17:17:02 +0100564
565/*-----------------------------------------------------------------------
566 * SCCR - System Clock Control 9-8
567 *-----------------------------------------------------------------------
568 * Ensure DFBRG is Divide by 16
569 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200570#define CONFIG_SYS_SCCR SCCR_DFBRG01
Heiko Schocher3ec43662006-12-21 17:17:02 +0100571
572/*-----------------------------------------------------------------------
573 * RCCR - RISC Controller Configuration 13-7
574 *-----------------------------------------------------------------------
575 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200576#define CONFIG_SYS_RCCR 0
Heiko Schocher3ec43662006-12-21 17:17:02 +0100577
578/*
579 * Init Memory Controller:
580 *
581 * Bank Bus Machine PortSz Device
582 * ---- --- ------- ------ ------
583 * 0 60x GPCM 32 bit FLASH
584 * 1 60x SDRAM 64 bit SDRAM
585 * 2 60x UPMB 8 bit NAND
Wolfgang Denk52e9f302006-12-24 01:42:57 +0100586 * 3 60x UPMC 8 bit CAN
Heiko Schocher3ec43662006-12-21 17:17:02 +0100587 *
588 */
589
590/* Initialize SDRAM
591 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200592#undef CONFIG_SYS_INIT_LOCAL_SDRAM /* No SDRAM on Local Bus */
Heiko Schocher3ec43662006-12-21 17:17:02 +0100593
594#define SDRAM_MAX_SIZE 0x20000000 /* max. 512 MB */
595
596/* Minimum mask to separate preliminary
597 * address ranges for CS[0:2]
598 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200599#define CONFIG_SYS_GLOBAL_SDRAM_LIMIT (512<<20) /* less than 512 MB */
Heiko Schocher3ec43662006-12-21 17:17:02 +0100600
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200601#define CONFIG_SYS_MPTPR 0x4000
Heiko Schocher3ec43662006-12-21 17:17:02 +0100602
603/*-----------------------------------------------------------------------------
604 * Address for Mode Register Set (MRS) command
605 *-----------------------------------------------------------------------------
606 * In fact, the address is rather configuration data presented to the SDRAM on
607 * its address lines. Because the address lines may be mux'ed externally either
608 * for 8 column or 9 column devices, some bits appear twice in the 8260's
609 * address:
610 *
611 * | (RFU) | (RFU) | WBL | TM | CL | BT | Burst Length |
612 * | BA1 BA0 | A12 : A10 | A9 | A8 A7 | A6 : A4 | A3 | A2 : A0 |
613 * 8 columns mux'ing: | A9 | A10 A21 | A22 : A24 | A25 | A26 : A28 |
614 * 9 columns mux'ing: | A8 | A20 A21 | A22 : A24 | A25 | A26 : A28 |
615 * Settings: | 0 | 0 0 | 0 1 0 | 0 | 0 1 0 |
616 *-----------------------------------------------------------------------------
617 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200618#define CONFIG_SYS_MRS_OFFS 0x00000110
Heiko Schocher3ec43662006-12-21 17:17:02 +0100619
Heiko Schocher3ec43662006-12-21 17:17:02 +0100620/* Bank 0 - FLASH
621 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200622#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK) |\
Heiko Schocher3ec43662006-12-21 17:17:02 +0100623 BRx_PS_32 |\
624 BRx_MS_GPCM_P |\
625 BRx_V)
626
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200627#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) |\
Heiko Schocher3ec43662006-12-21 17:17:02 +0100628 ORxG_CSNT |\
629 ORxG_ACS_DIV4 |\
630 ORxG_SCY_8_CLK |\
631 ORxG_TRLX)
632
633/* SDRAM on TQM8272 can have either 8 or 9 columns.
634 * The number affects configuration values.
635 */
636
637/* Bank 1 - 60x bus SDRAM
638 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200639#define CONFIG_SYS_PSRT 0x20 /* Low Value */
640/* #define CONFIG_SYS_PSRT 0x10 Fast Value */
641#define CONFIG_SYS_LSRT 0x20 /* Local Bus */
642#ifndef CONFIG_SYS_RAMBOOT
643#define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK) |\
Heiko Schocher3ec43662006-12-21 17:17:02 +0100644 BRx_PS_64 |\
645 BRx_MS_SDRAM_P |\
646 BRx_V)
647
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200648#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR1_8COL
Heiko Schocher3ec43662006-12-21 17:17:02 +0100649
650/* SDRAM initialization values for 8-column chips
651 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200652#define CONFIG_SYS_OR1_8COL ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
Heiko Schocher3ec43662006-12-21 17:17:02 +0100653 ORxS_BPD_4 |\
654 ORxS_ROWST_PBI1_A7 |\
655 ORxS_NUMR_12)
656
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200657#define CONFIG_SYS_PSDMR_8COL (PSDMR_PBI |\
Heiko Schocher3ec43662006-12-21 17:17:02 +0100658 PSDMR_SDAM_A15_IS_A5 |\
659 PSDMR_BSMA_A12_A14 |\
660 PSDMR_SDA10_PBI1_A8 |\
661 PSDMR_RFRC_7_CLK |\
662 PSDMR_PRETOACT_2W |\
663 PSDMR_ACTTORW_2W |\
664 PSDMR_LDOTOPRE_1C |\
665 PSDMR_WRC_2C |\
666 PSDMR_EAMUX |\
667 PSDMR_BUFCMD |\
668 PSDMR_CL_2)
669
670
671/* SDRAM initialization values for 9-column chips
672 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200673#define CONFIG_SYS_OR1_9COL ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
Heiko Schocher3ec43662006-12-21 17:17:02 +0100674 ORxS_BPD_4 |\
675 ORxS_ROWST_PBI1_A5 |\
676 ORxS_NUMR_13)
677
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200678#define CONFIG_SYS_PSDMR_9COL (PSDMR_PBI |\
Heiko Schocher3ec43662006-12-21 17:17:02 +0100679 PSDMR_SDAM_A16_IS_A5 |\
680 PSDMR_BSMA_A12_A14 |\
681 PSDMR_SDA10_PBI1_A7 |\
682 PSDMR_RFRC_7_CLK |\
683 PSDMR_PRETOACT_2W |\
684 PSDMR_ACTTORW_2W |\
685 PSDMR_LDOTOPRE_1C |\
686 PSDMR_WRC_2C |\
687 PSDMR_EAMUX |\
688 PSDMR_BUFCMD |\
689 PSDMR_CL_2)
690
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200691#define CONFIG_SYS_OR1_10COL ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
Heiko Schocher3ec43662006-12-21 17:17:02 +0100692 ORxS_BPD_4 |\
693 ORxS_ROWST_PBI1_A4 |\
694 ORxS_NUMR_13)
695
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200696#define CONFIG_SYS_PSDMR_10COL (PSDMR_PBI |\
Heiko Schocher3ec43662006-12-21 17:17:02 +0100697 PSDMR_SDAM_A17_IS_A5 |\
698 PSDMR_BSMA_A12_A14 |\
699 PSDMR_SDA10_PBI1_A4 |\
700 PSDMR_RFRC_6_CLK |\
701 PSDMR_PRETOACT_2W |\
702 PSDMR_ACTTORW_2W |\
703 PSDMR_LDOTOPRE_1C |\
704 PSDMR_WRC_2C |\
705 PSDMR_EAMUX |\
706 PSDMR_BUFCMD |\
707 PSDMR_CL_2)
708
Heiko Schocher3ec43662006-12-21 17:17:02 +0100709#define PSDMR_RFRC_66MHZ_SINGLE 0x00028000 /* PSDMR[RFRC] at 66 MHz single mode */
710#define PSDMR_RFRC_100MHZ_SINGLE 0x00030000 /* PSDMR[RFRC] at 100 MHz single mode */
711#define PSDMR_RFRC_133MHZ_SINGLE 0x00030000 /* PSDMR[RFRC] at 133 MHz single mode */
712#define PSDMR_RFRC_66MHZ_60X 0x00030000 /* PSDMR[RFRC] at 66 MHz 60x mode */
713#define PSDMR_RFRC_100MHZ_60X 0x00028000 /* PSDMR[RFRC] at 100 MHz 60x mode */
714#define PSDMR_RFRC_DEFAULT PSDMR_RFRC_133MHZ_SINGLE /* PSDMR[RFRC] default value */
715
716#define PSDMR_PRETOACT_66MHZ_SINGLE 0x00002000 /* PSDMR[PRETOACT] at 66 MHz single mode */
717#define PSDMR_PRETOACT_100MHZ_SINGLE 0x00002000 /* PSDMR[PRETOACT] at 100 MHz single mode */
718#define PSDMR_PRETOACT_133MHZ_SINGLE 0x00002000 /* PSDMR[PRETOACT] at 133 MHz single mode */
719#define PSDMR_PRETOACT_66MHZ_60X 0x00001000 /* PSDMR[PRETOACT] at 66 MHz 60x mode */
720#define PSDMR_PRETOACT_100MHZ_60X 0x00001000 /* PSDMR[PRETOACT] at 100 MHz 60x mode */
721#define PSDMR_PRETOACT_DEFAULT PSDMR_PRETOACT_133MHZ_SINGLE /* PSDMR[PRETOACT] default value */
722
723#define PSDMR_WRC_66MHZ_SINGLE 0x00000020 /* PSDMR[WRC] at 66 MHz single mode */
724#define PSDMR_WRC_100MHZ_SINGLE 0x00000020 /* PSDMR[WRC] at 100 MHz single mode */
725#define PSDMR_WRC_133MHZ_SINGLE 0x00000010 /* PSDMR[WRC] at 133 MHz single mode */
726#define PSDMR_WRC_66MHZ_60X 0x00000010 /* PSDMR[WRC] at 66 MHz 60x mode */
727#define PSDMR_WRC_100MHZ_60X 0x00000010 /* PSDMR[WRC] at 100 MHz 60x mode */
728#define PSDMR_WRC_DEFAULT PSDMR_WRC_133MHZ_SINGLE /* PSDMR[WRC] default value */
729
730#define PSDMR_BUFCMD_66MHZ_SINGLE 0x00000000 /* PSDMR[BUFCMD] at 66 MHz single mode */
731#define PSDMR_BUFCMD_100MHZ_SINGLE 0x00000000 /* PSDMR[BUFCMD] at 100 MHz single mode */
732#define PSDMR_BUFCMD_133MHZ_SINGLE 0x00000004 /* PSDMR[BUFCMD] at 133 MHz single mode */
733#define PSDMR_BUFCMD_66MHZ_60X 0x00000000 /* PSDMR[BUFCMD] at 66 MHz 60x mode */
734#define PSDMR_BUFCMD_100MHZ_60X 0x00000000 /* PSDMR[BUFCMD] at 100 MHz 60x mode */
735#define PSDMR_BUFCMD_DEFAULT PSDMR_BUFCMD_133MHZ_SINGLE /* PSDMR[BUFCMD] default value */
736
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200737#endif /* CONFIG_SYS_RAMBOOT */
Heiko Schocher3ec43662006-12-21 17:17:02 +0100738
739#endif /* __CONFIG_H */