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TsiChung Liewf6afe722007-06-18 13:50:13 -05001/*
2 * Configuation settings for the Freescale MCF5329 FireEngine board.
3 *
4 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
6 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02007 * SPDX-License-Identifier: GPL-2.0+
TsiChung Liewf6afe722007-06-18 13:50:13 -05008 */
9
10/*
11 * board/config.h - configuration options, board specific
12 */
13
14#ifndef _M5329EVB_H
15#define _M5329EVB_H
16
17/*
18 * High Level Configuration Options
19 * (easy to change)
20 */
21#define CONFIG_MCF532x /* define processor family */
22#define CONFIG_M5329 /* define processor type */
23
TsiChungLiewdb0022d2007-08-05 03:19:10 -050024#define CONFIG_MCFUART
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020025#define CONFIG_SYS_UART_PORT (0)
TsiChung Liewf6afe722007-06-18 13:50:13 -050026#define CONFIG_BAUDRATE 115200
TsiChung Liewf6afe722007-06-18 13:50:13 -050027
28#undef CONFIG_WATCHDOG
29#define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */
30
TsiChungLiewaedd3d72007-08-15 15:39:17 -050031/* Command line configuration */
32#include <config_cmd_default.h>
33
34#define CONFIG_CMD_CACHE
35#define CONFIG_CMD_DATE
36#define CONFIG_CMD_ELF
37#define CONFIG_CMD_FLASH
38#define CONFIG_CMD_I2C
39#define CONFIG_CMD_MEMORY
40#define CONFIG_CMD_MISC
41#define CONFIG_CMD_MII
42#define CONFIG_CMD_NET
43#define CONFIG_CMD_PING
44#define CONFIG_CMD_REGINFO
TsiChung6373c0c2007-07-10 15:45:43 -050045
stany MARCEL5ac9ea62011-10-19 00:17:13 +080046#ifdef CONFIG_NANDFLASH_SIZE
TsiChungLiewaedd3d72007-08-15 15:39:17 -050047# define CONFIG_CMD_NAND
TsiChungLiewec8468f2007-08-05 04:31:18 -050048#endif
49
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020050#define CONFIG_SYS_UNIFY_CACHE
TsiChung Liewf6afe722007-06-18 13:50:13 -050051
52#define CONFIG_MCFFEC
53#ifdef CONFIG_MCFFEC
TsiChung Liewf6afe722007-06-18 13:50:13 -050054# define CONFIG_MII 1
TsiChung Liewb3162452008-03-30 01:22:13 -050055# define CONFIG_MII_INIT 1
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020056# define CONFIG_SYS_DISCOVER_PHY
57# define CONFIG_SYS_RX_ETH_BUFFER 8
58# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
TsiChung Liewf6afe722007-06-18 13:50:13 -050059
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020060# define CONFIG_SYS_FEC0_PINMUX 0
61# define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
Wolfgang Denka1be4762008-05-20 16:00:29 +020062# define MCFFEC_TOUT_LOOP 50000
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020063/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
64# ifndef CONFIG_SYS_DISCOVER_PHY
TsiChung Liewf6afe722007-06-18 13:50:13 -050065# define FECDUPLEX FULL
66# define FECSPEED _100BASET
67# else
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020068# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
69# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
TsiChung Liewf6afe722007-06-18 13:50:13 -050070# endif
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020071# endif /* CONFIG_SYS_DISCOVER_PHY */
TsiChung Liewf6afe722007-06-18 13:50:13 -050072#endif
73
TsiChung Liewf6afe722007-06-18 13:50:13 -050074#define CONFIG_MCFRTC
TsiChungLiew2e0aeef2007-07-05 22:39:07 -050075#undef RTC_DEBUG
TsiChung Liewf6afe722007-06-18 13:50:13 -050076
77/* Timer */
78#define CONFIG_MCFTMR
TsiChung Liewf6afe722007-06-18 13:50:13 -050079#undef CONFIG_MCFPIT
TsiChung Liewf6afe722007-06-18 13:50:13 -050080
TsiChungLiew876343b2007-08-05 04:11:20 -050081/* I2C */
Heiko Schocherf2850742012-10-24 13:48:22 +020082#define CONFIG_SYS_I2C
83#define CONFIG_SYS_I2C_FSL
84#define CONFIG_SYS_FSL_I2C_SPEED 80000
85#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
86#define CONFIG_SYS_FSL_I2C_OFFSET 0x58000
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020087#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
TsiChungLiew876343b2007-08-05 04:11:20 -050088
TsiChung Liewf6afe722007-06-18 13:50:13 -050089#define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */
TsiChungLiewaedd3d72007-08-15 15:39:17 -050090#define CONFIG_UDP_CHECKSUM
91
TsiChung Liewf6afe722007-06-18 13:50:13 -050092#ifdef CONFIG_MCFFEC
TsiChungLiew876343b2007-08-05 04:11:20 -050093# define CONFIG_ETHADDR 00:e0:0c:bc:e5:60
94# define CONFIG_IPADDR 192.162.1.2
95# define CONFIG_NETMASK 255.255.255.0
96# define CONFIG_SERVERIP 192.162.1.1
TsiChung Liewf6afe722007-06-18 13:50:13 -050097# define CONFIG_GATEWAYIP 192.162.1.1
98# define CONFIG_OVERWRITE_ETHADDR_ONCE
99#endif /* FEC_ENET */
100
101#define CONFIG_HOSTNAME M5329EVB
102#define CONFIG_EXTRA_ENV_SETTINGS \
103 "netdev=eth0\0" \
104 "loadaddr=40010000\0" \
105 "u-boot=u-boot.bin\0" \
106 "load=tftp ${loadaddr) ${u-boot}\0" \
107 "upd=run load; run prog\0" \
Jason Jinded4eb42011-08-19 10:10:40 +0800108 "prog=prot off 0 3ffff;" \
109 "era 0 3ffff;" \
TsiChung Liewf6afe722007-06-18 13:50:13 -0500110 "cp.b ${loadaddr} 0 ${filesize};" \
111 "save\0" \
112 ""
113
TsiChungLiew876343b2007-08-05 04:11:20 -0500114#define CONFIG_PRAM 512 /* 512 KB */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200115#define CONFIG_SYS_PROMPT "-> "
116#define CONFIG_SYS_LONGHELP /* undef to save memory */
TsiChung Liewf6afe722007-06-18 13:50:13 -0500117
TsiChungLiewaedd3d72007-08-15 15:39:17 -0500118#ifdef CONFIG_CMD_KGDB
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200119# define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
TsiChung Liewf6afe722007-06-18 13:50:13 -0500120#else
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200121# define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
TsiChung Liewf6afe722007-06-18 13:50:13 -0500122#endif
123
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200124#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
125#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
126#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
127#define CONFIG_SYS_LOAD_ADDR 0x40010000
TsiChung Liewf6afe722007-06-18 13:50:13 -0500128
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200129#define CONFIG_SYS_HZ 1000
130#define CONFIG_SYS_CLK 80000000
131#define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 3
TsiChung Liewf6afe722007-06-18 13:50:13 -0500132
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200133#define CONFIG_SYS_MBAR 0xFC000000
TsiChung Liewf6afe722007-06-18 13:50:13 -0500134
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200135#define CONFIG_SYS_LATCH_ADDR (CONFIG_SYS_CS1_BASE + 0x80000)
TsiChungLiewec8468f2007-08-05 04:31:18 -0500136
TsiChung Liewf6afe722007-06-18 13:50:13 -0500137/*
138 * Low Level Configuration Settings
139 * (address mappings, register initial values, etc.)
140 * You should know what you are doing if you make changes here.
141 */
142/*-----------------------------------------------------------------------
143 * Definitions for initial stack pointer and data area (in DPRAM)
144 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200145#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
Wolfgang Denk1c2e98e2010-10-26 13:32:32 +0200146#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200147#define CONFIG_SYS_INIT_RAM_CTRL 0x221
Wolfgang Denk0191e472010-10-26 14:34:52 +0200148#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200149#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
TsiChung Liewf6afe722007-06-18 13:50:13 -0500150
151/*-----------------------------------------------------------------------
152 * Start addresses for the final memory configuration
153 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200154 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
TsiChung Liewf6afe722007-06-18 13:50:13 -0500155 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200156#define CONFIG_SYS_SDRAM_BASE 0x40000000
157#define CONFIG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */
158#define CONFIG_SYS_SDRAM_CFG1 0x53722730
159#define CONFIG_SYS_SDRAM_CFG2 0x56670000
160#define CONFIG_SYS_SDRAM_CTRL 0xE1092000
161#define CONFIG_SYS_SDRAM_EMOD 0x40010000
162#define CONFIG_SYS_SDRAM_MODE 0x018D0000
TsiChung Liewf6afe722007-06-18 13:50:13 -0500163
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200164#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400
165#define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
TsiChung Liewf6afe722007-06-18 13:50:13 -0500166
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200167#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
168#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
TsiChung Liewf6afe722007-06-18 13:50:13 -0500169
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200170#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
171#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
TsiChung Liewf6afe722007-06-18 13:50:13 -0500172
173/*
174 * For booting Linux, the board info and command line data
175 * have to be in the first 8 MB of memory, since this is
176 * the maximum mapped by the Linux kernel during initialization ??
177 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200178#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
TsiChung Liew25a00632009-01-27 12:57:47 +0000179#define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20)
TsiChung Liewf6afe722007-06-18 13:50:13 -0500180
181/*-----------------------------------------------------------------------
182 * FLASH organization
183 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200184#define CONFIG_SYS_FLASH_CFI
185#ifdef CONFIG_SYS_FLASH_CFI
Jean-Christophe PLAGNIOL-VILLARD8d94c232008-08-13 01:40:42 +0200186# define CONFIG_FLASH_CFI_DRIVER 1
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200187# define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */
188# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
189# define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
190# define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
191# define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
TsiChung Liewf6afe722007-06-18 13:50:13 -0500192#endif
193
stany MARCEL5ac9ea62011-10-19 00:17:13 +0800194#ifdef CONFIG_NANDFLASH_SIZE
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200195# define CONFIG_SYS_MAX_NAND_DEVICE 1
196# define CONFIG_SYS_NAND_BASE CONFIG_SYS_CS2_BASE
197# define CONFIG_SYS_NAND_SIZE 1
198# define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
TsiChungLiewaedd3d72007-08-15 15:39:17 -0500199# define NAND_ALLOW_ERASE_ALL 1
200# define CONFIG_JFFS2_NAND 1
201# define CONFIG_JFFS2_DEV "nand0"
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200202# define CONFIG_JFFS2_PART_SIZE (CONFIG_SYS_CS2_MASK & ~1)
TsiChungLiewaedd3d72007-08-15 15:39:17 -0500203# define CONFIG_JFFS2_PART_OFFSET 0x00000000
TsiChungLiewec8468f2007-08-05 04:31:18 -0500204#endif
205
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200206#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
TsiChung Liewf6afe722007-06-18 13:50:13 -0500207
208/* Configuration for environment
209 * Environment is embedded in u-boot in the second sector of the flash
210 */
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +0200211#define CONFIG_ENV_OFFSET 0x4000
212#define CONFIG_ENV_SECT_SIZE 0x2000
Jean-Christophe PLAGNIOL-VILLARD53db4cd2008-09-10 22:48:04 +0200213#define CONFIG_ENV_IS_IN_FLASH 1
TsiChung Liewf6afe722007-06-18 13:50:13 -0500214
215/*-----------------------------------------------------------------------
216 * Cache Configuration
217 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200218#define CONFIG_SYS_CACHELINE_SIZE 16
TsiChung Liewf6afe722007-06-18 13:50:13 -0500219
TsiChung Liew0ee47d42010-03-11 22:12:53 -0600220#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
Wolfgang Denk1c2e98e2010-10-26 13:32:32 +0200221 CONFIG_SYS_INIT_RAM_SIZE - 8)
TsiChung Liew0ee47d42010-03-11 22:12:53 -0600222#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
Wolfgang Denk1c2e98e2010-10-26 13:32:32 +0200223 CONFIG_SYS_INIT_RAM_SIZE - 4)
TsiChung Liew0ee47d42010-03-11 22:12:53 -0600224#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA)
225#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
226 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
227 CF_ACR_EN | CF_ACR_SM_ALL)
228#define CONFIG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \
229 CF_CACR_DCM_P)
230
TsiChung Liewf6afe722007-06-18 13:50:13 -0500231/*-----------------------------------------------------------------------
232 * Chipselect bank definitions
233 */
234/*
235 * CS0 - NOR Flash 1, 2, 4, or 8MB
236 * CS1 - CompactFlash and registers
237 * CS2 - NAND Flash 16, 32, or 64MB
238 * CS3 - Available
239 * CS4 - Available
240 * CS5 - Available
241 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200242#define CONFIG_SYS_CS0_BASE 0
243#define CONFIG_SYS_CS0_MASK 0x007f0001
244#define CONFIG_SYS_CS0_CTRL 0x00001fa0
TsiChung Liewf6afe722007-06-18 13:50:13 -0500245
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200246#define CONFIG_SYS_CS1_BASE 0x10000000
247#define CONFIG_SYS_CS1_MASK 0x001f0001
248#define CONFIG_SYS_CS1_CTRL 0x002A3780
TsiChung Liewf6afe722007-06-18 13:50:13 -0500249
stany MARCEL5ac9ea62011-10-19 00:17:13 +0800250#ifdef CONFIG_NANDFLASH_SIZE
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200251#define CONFIG_SYS_CS2_BASE 0x20000000
stany MARCEL5ac9ea62011-10-19 00:17:13 +0800252#define CONFIG_SYS_CS2_MASK ((CONFIG_NANDFLASH_SIZE << 20) | 1)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200253#define CONFIG_SYS_CS2_CTRL 0x00001f60
TsiChung Liewf6afe722007-06-18 13:50:13 -0500254#endif
255
TsiChung Liewf6afe722007-06-18 13:50:13 -0500256#endif /* _M5329EVB_H */